IS43/46TR16512B, IS43/46TR16512BL,
IS43/46TR81024B, IS43/46TR81024BL
1Gx8, 512Mx16 8Gb DDR3 SDRAM
JUNE 2018
PRELIMINARY INFORMATION
FEATURES
Standard Voltage:
V
DD
and V
DDQ
= 1.5V ± 0.075V
Low Voltage (L):
V
DD
and V
DDQ
= 1.35V + 0.1V, -0.067V
- Backward compatible to 1.5V
High speed data transfer rates with system
frequency up to 1066 MHz
8 internal banks for concurrent operation
8n-Bit pre-fetch architecture
Programmable CAS Latency
Programmable Additive Latency: 0, CL-1,CL-2
Programmable CAS WRITE latency (CWL) based
on tCK
Programmable Burst Length: 4 and 8
Programmable Burst Sequence: Sequential or
Interleave
BL switch on the fly
Auto Self Refresh(ASR)
Self Refresh Temperature(SRT)
Refresh Interval:
7.8 us (8192 cycles/64 ms) Tc= -40°C to 85°C
3.9 us (8192 cycles/32 ms) Tc= 85°C to 105°C
Partial Array Self Refresh
Asynchronous RESET pin
TDQS (Termination Data Strobe) supported (x8
only)
OCD (Off-Chip Driver Impedance Adjustment)
Dynamic ODT (On-Die Termination)
Driver strength : RZQ/7, RZQ/6 (RZQ = 240 Ω)
Write Leveling
Up to 200 MHz in DLL off mode
Operating temperature:
Commercial (T
C
= 0°C to +95°C)
Industrial (T
C
= -40°C to +95°C)
Automotive, A1 (T
C
= -40°C to +95°C)
Automotive, A2 (T
C
= -40°C to +105°C)
OPTIONS
Configuration:
1Gx8
512Mx16
Package:
96-ball BGA (10mm x 14mm) for x16
78-ball BGA (10mm x 14mm) for x8
ADDRESS TABLE
Parameter
Row Addressing
Column Addressing
Bank Addressing
Page size
Auto Precharge
Addressing
BL switch on the fly
1Gx8
A0-A15
A0-A9, A11
BA0-2
2KB
A10/AP
A12/BC#
512Mx16
A0-A15
A0-A9
BA0-2
2KB
A10/AP
A12/BC#
SPEED BIN
Speed Option
JEDEC Speed Grade
CL-nRCD-nRP
tRCD,tRP(min)
125K
DDR3-1600K
11-11-11
13.75
107M
DDR3-1866M
13-13-13
13.91
093N
Units
DDR3-2133N
14-14-14
13.09
tCK
ns
Note: Faster speed options are backward compatible to slower speed options.
Copyright © 2018 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised
to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product
can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use
in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc.
– www.issi.com –
Rev. 0A
02/05/2018
1
IS43/46TR16512B, IS43/46TR16512BL,
IS43/46TR81024B, IS43/46TR81024BL
1.3 Pinout Description - JEDEC Standard
Symbol
CK, CK#
CKE
Type
Input
Input
Function
Clock: CK and CK# are differential clock inputs. All address and control input signals are
sampled on the crossing of the positive edge of CK and negative edge of CK#.
Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and
device input buffers and output drivers. Taking CKE Low provides Precharge Power-Down and
Self-Refresh operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is
asynchronous for Self-Refresh exit. After VREFCA and VREFDQ have become stable during
the power on and initialization sequence, they must be maintained during all operations
(including Self-Refresh). CKE must be maintained high throughout read and write accesses.
Input buffers, excluding CK, CK#, ODT and CKE, are disabled during power-down. Input
buffers, excluding CKE, are disabled during Self-Refresh.
Chip Select: All commands are masked when CS# is registered HIGH. CS# provides for
external Rank selection on systems with multiple Ranks. CS# is considered part of the
command code.
On Die Termination: ODT (registered HIGH) enables termination resistance internal to the
DDR3 SDRAM. When enabled, ODT is only applied to each DQ, DQSU, DQSU#, DQSL,
DQSL#, DMU, and DML signal. The ODT pin will be ignored if MR1 and MR2 are programmed
to disable RTT.
Command Inputs: RAS#, CAS# and WE# (along with CS#) define the command being entered.
Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is
sampled HIGH coincident with that input data during a Write access. DM is sampled on both
edges of DQS. For x8 device, the function of DM or TDQS/TDQS# is enabled by Mode
Register A11 setting in MR1.
Bank Address Inputs: BA0 - BA2 define to which bank an Active, Read, Write, or Precharge
command is being applied. Bank address also determines which mode register is to be
accessed during a MRS cycle.
Address Inputs: Provide the row address for Active commands and the column address for
Read/ Write commands to select one location out of the memory array in the respective bank.
(A10/AP and A12/BC# have additional functions; see below). The address inputs also provide
the op-code during Mode Register Set commands.
Auto-precharge: A10 is sampled during Read/Write commands to determine whether
Autoprecharge should be performed to the accessed bank after the Read/Write operation.
(HIGH: Autoprecharge; LOW: no Autoprecharge). A10 is sampled during a Precharge
command to determine whether the Precharge applies to one bank (A10 LOW) or all banks
(A10 HIGH). If only one bank is to be precharged, the bank is selected by bank addresses.
Burst Chop: A12 / BC# is sampled during Read and Write commands to determine if burst
chop (on-the-fly) will be performed. (HIGH, no burst chop; LOW: burst chopped). See
command truth table for details.
Active Low Asynchronous Reset: Reset is active when RESET# is LOW, and inactive when
RESET# is HIGH. RESET# must be HIGH during normal operation. RESET# is a CMOS rail-
to-rail signal with DC high and low at 80% and 20% of VDD, i.e., 1.20V for DC high and 0.30V
for DC low.
Data Input/ Output: Bi-directional data bus.
Data Strobe: output with read data, input with write data. Edge-aligned with read data, centered
in write data. For the x16, DQSL corresponds to the data on DQL0-DQL7; DQSU corresponds
to the data on DQU0-DQU7. The data strobes DQS, DQSL, and DQSU are paired with
differential signals DQS#, DQSL#, and DQSU#, respectively, to provide differential pair
signaling to the system during reads and writes. DDR3 SDRAM supports differential data
strobe only and does not support single-ended.
Termination Data Strobe: TDQS/TDQS# is applicable for x8 DRAMs only. When enabled via
Mode Register A11 = 1 in MR1, the DRAM will enable the same termination resistance function
on TDQS/TDQS# that is applied to DQS/DQS#. When disabled via mode register A11 = 0 in
MR1, DM/TDQS will provide the data mask function and TDQS# is not used. x16 DRAMs must
disable the TDQS function via mode register A11 = 0 in MR1.
CS#
Input
ODT
Input
RAS#. CAS#.
WE#
DM, (DMU),
(DML)
Input
Input
BA0 - BA2
Input
A0 - A15
Input
A10 / AP
Input
A12 / BC#
Input
RESET#
Input
DQ( DQL, DQU)
DQS,
DQS#, DQSU,
DQSU#, DQSL,
DQSL#
Input /
Output
Input /
Output
TDQS, TDQS#
Output
Integrated Silicon Solution, Inc.
– www.issi.com –
Rev. 0A
02/05/2018
4
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