dsPIC33CK64MP203-I/M5 datasheet, PDF

Datasheet> All Categories > semiconductor> The embedded processor and controller> Digital signal processor and controller - DSP, DSC> dsPIC33CK64MP203-I/M5

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dsPIC33CK64MP203-I/M5: DescriptionDigital Signal Processor and Controller - DSP, DSC 16 Bit DSC, 64KB Flash, 8KB RAM, 100MHz, 28Pin, 3 OpAmp, 3 Comp, PTG; Categorysemiconductor The embedded processor and controller Digital signal processor and controller - DSP, DSC; File Size4MB，621 Pages; ManufacturerMicrochip; Websitehttps://www.microchip.com; Environmental Compliance

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dsPIC33CK64MP203-I/M5 Overview

Digital Signal Processor and Controller - DSP, DSC 16 Bit DSC, 64KB Flash, 8KB RAM, 100MHz, 28Pin, 3 OpAmp, 3 Comp, PTG

dsPIC33CK64MP203-I/M5 Parametric

Parameter Name	Attribute value
Maker	Microchip
Product Category	Digital Signal Processors and Controllers - DSP, DSC
Installation style	SMD/SMT
Package/box	UQFN-36
series	dsPIC33CK
product	DSCs
core	dsPIC33CK
maximum clock frequency	100 MHz
Program memory size	64 kB
Data RAM size	8 kB
Working power voltage	3 V to 3.6 V
Minimum operating temperature	- 40 C
Maximum operating temperature	+ 85 C
Encapsulation	Tube
Program memory type	Flash
Interface Type	CAN, I2C, I2S, SPI, UART
Data bus width	16 bit
Instruction type	Fixed/Floating Point
Number of cores	1 Core
Number of timers/counters	1 Timer
Factory packaging quantity	73
Supply voltage - max.	3.6 V
Supply voltage - min.	3 V
watchdog timer	Watchdog Timer

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dsPIC33CK256MP508 FAMILY

28/36/48/64/80-Pin, 16-Bit Digital Signal Controllers

with High-Resolution PWM and CAN Flexible Data (CAN FD)

Operating Conditions

• 3.0V to 3.6V, -40°C to +85°C, DC to 100 MIPS

• 3.0V to 3.6V, -40°C to +125°C, DC to 100 MIPS

Power Management

• Low-Power Management Modes (Sleep,

Idle, Doze)

• Integrated Power-on Reset and Brown-out Reset

Core: 16-Bit dsPIC33CK CPU

• 32-256 Kbytes of Program Flash with ECC and

8-24K RAM

• Fast 6-Cycle Divide

• LiveUpdate

• Code Efficient (C and Assembly) Architecture

• 40-Bit Wide Accumulators

• Single-Cycle (MAC/MPY) with Dual Data Fetch

• Single-Cycle, Mixed-Sign MUL Plus

Hardware Divide

• 32-Bit Multiply Support

• Four Sets of Interrupt Context Saving Registers

which Include Accumulator and STATUS for Fast

Interrupt Handling

• Zero Overhead Looping

• RAM Memory Built-In Self-Test (MBIST)

High-Speed PWM

8 PWM Pairs

Up to 250 ps PWM Resolution

Dead Time for Rising and Falling Edges

Dead-Time Compensation

Clock Chopping for High-Frequency Operation

PWM Support for:

- DC/DC, AC/DC, inverters, PFC, lighting

- BLDC, PMSM, ACIM, SRM motors

• Fault and Current Limit Inputs

• Flexible Trigger Configuration for ADC Triggering

•

Timers/Output Compare/Input Capture

• One General Purpose Timer

• Peripheral Trigger Generator (PTG):

- Up to 15 trigger sources to other

peripheral modules

- CPU independent state machine-based

instruction sequencer

• Nine MCCP/SCCP modules which Include Timer,

Capture/Compare and PWM:

- 1 MCCP

- 8 SCCPs

- 16 or 32-bit time base

- 16 or 32-bit capture

- 4-deep capture buffer

• Fully Asynchronous Operation, Available in

Sleep Modes

Clock Management

•

Internal Oscillator

Programmable PLLs and Oscillator Clock Sources

Reference Clock Output

Fail-Safe Clock Monitor (FSCM)

Fast Wake-up and Start-up

Backup Internal Oscillator



2017-2018 Microchip Technology Inc.

Advance Information

DS70005349B-page 1

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