Data Sheet
FEATURES
Supports Stratum 2 stability in holdover mode
Supports reference switchover with phase build-out
Supports hitless reference switchover
Automatic/manual holdover and reference switchover
2 pairs of reference input pins, with each pair configurable
as a single differential input or as 2 independent single-
ended inputs
Input reference frequencies from 1 kHz to 750 MHz
Reference validation and frequency monitoring (1 ppm)
Programmable input reference switchover priority
30-bit programmable input reference divider
2 pairs of clock output pins, with each pair configurable as
a single differential LVDS/LVPECL output or as 2 single-
ended CMOS outputs
Output frequencies up to 450 MHz
20-bit integer and 10-bit fractional programmable feedback
divider
Programmable digital loop filter covering loop bandwidths
from 0.001 Hz to 100 kHz
Optional low noise LC-VCO system clock multiplier
Optional crystal resonator for system clock input
On-chip EEPROM to store multiple power-up profiles
Software controlled power-down
64-lead LFCSP package
Dual/Quad Input Network Clock
Generator/Synchronizer
AD9547
APPLICATIONS
Network synchronization
Cleanup of reference clock jitter
SONET/SDH clocks up to OC-192, including FEC
Stratum 2 holdover, jitter cleanup, and phase transient
control
Stratum 3E and Stratum 3 reference clocks
Wireless base stations, controllers
Cable infrastructure
Data communications
GENERAL DESCRIPTION
The
AD9547
provides synchronization for many systems,
including synchronous optical networks (SONET/SDH). The
AD9547
generates an output clock that is synchronized to one
of two differential or four single-ended external input references.
The digital PLL allows for reduction of input time jitter or phase
noise associated with the external references. The
AD9547
continuously generates a clean (low jitter), valid output clock,
even when all references fail, by means of digitally controlled
loop and holdover circuitry.
The
AD9547
operates over an industrial temperature range of
−40°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
STABLE
SOURCE
ANALOG
FILTER
AD9547
CLOCK
MULTIPLIER
CLOCK DISTRIBUTION
CHANNEL 0
DIVIDER
DIGITAL
PLL
REFERENCE INPUTS
AND
MONITOR MUX
SYNC
DAC
CHANNEL 1
DIVIDER
SERIAL CONTROL INTERFACE
(SPI or I
2
C)
EEPROM
STATUS AND
CONTROL PINS
08300-001
Figure 1.
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
Rev. G
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AD9547
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 3
Specifications..................................................................................... 4
Supply Voltage ............................................................................... 4
Supply Current .............................................................................. 4
Power Dissipation ......................................................................... 4
Logic Inputs (M0 to M7, RESET)............................................... 5
Logic Outputs (M0 to M7, IRQ) ................................................ 5
System Clock Inputs (SYSCLKP, SYSCLKN)............................ 5
Distribution Clock Inputs (CLKINP, CLKINN) ...................... 6
Reference Inputs (REFA/REFAA, REFB/REFBB) .................... 7
Reference Monitors ...................................................................... 7
Reference Switchover Specifications .......................................... 8
Distribution Clock Outputs (OUT0, OUT1) ........................... 8
DAC Output Characteristics (DACOUTP, DACOUTN) ....... 9
Time Duration of Digital Functions ........................................ 10
Digital PLL .................................................................................. 10
Digital PLL Lock Detection ...................................................... 10
Holdover Specifications ............................................................. 10
Serial Port Specifications—SPI Mode ...................................... 11
Serial Port Specifications—I
2
C Mode ...................................... 12
Jitter Generation ......................................................................... 13
Absolute Maximum Ratings.......................................................... 14
ESD Caution ................................................................................ 14
Pin Configuration and Function Descriptions ........................... 15
Typical Performance Characteristics ........................................... 18
Input/Output Termination Recommendations .......................... 23
Getting Started ................................................................................ 24
Power-On Reset .......................................................................... 24
Initial M0 to M7 Pin Programming ......................................... 24
Device Register Programming .................................................. 24
Theory of Operation ...................................................................... 26
Overview...................................................................................... 26
Reference Clock Inputs .............................................................. 27
Reference Monitors .................................................................... 27
Reference Profiles ....................................................................... 28
Reference Switchover ................................................................. 30
Data Sheet
Digital Phase-Locked Loop (DPLL) Core............................... 32
Direct Digital Synthesizer (DDS) ............................................. 34
Tuning Word Processing ........................................................... 35
Loop Control State Machine ..................................................... 36
System Clock Inputs................................................................... 37
SYSCLK PLL Multiplier............................................................. 38
Clock Distribution ..................................................................... 39
Status and Control .......................................................................... 44
Multifunction Pins (M0 to M7) ............................................... 44
IRQ Pin ........................................................................................ 45
Watchdog Timer ......................................................................... 45
EEPROM ..................................................................................... 46
Serial Control Port ......................................................................... 51
SPI/I
2
C Port Selection ................................................................ 51
SPI Serial Port Operation .......................................................... 51
I
2
C Serial Port Operation .......................................................... 56
I/O Programming Registers .......................................................... 59
Buffered/Active Registers .......................................................... 59
Autoclearing Registers ............................................................... 59
Register Access Restrictions...................................................... 59
Register Map ................................................................................... 60
Register Bit Descriptions ............................................................... 70
Serial Port Configuration and Part Identification
(Register 0x0000 to Register 0x0005) ...................................... 70
System Clock (SYSCLK) (Register 0x0100 to
Register 0x0108)..........................................................................
71
General Configuration (Register 0x0200 to
Register 0x0214)..........................................................................
72
DPLL Configuration (Register 0x0300 to Register 0x031B) ..... 75
Clock Distribution Output Configuration (Register 0x0400
to
Register 0x0417) ......... ........................................................... 77
Reference Input Configuration (Register 0x0500 to
Register 0x0507) .......................................................................... 79
Profile Registers (Register 0x0600 to Register 0x07FF) ........ 81
Operational Controls (Register 0x0A00 to
Register 0x0A10).........................................................................
90
Clock Part Serial ID (Register 0x0C00 to Register 0x0C07) ..... 94
Status Readback (Register 0x0D00 to Register 0x0D19) ...... 95
Nonvolatile Memory (EEPROM) Control (Register 0x0E00
to
Register 0x0E03) .................................................................... 97
EEPROM Storage Sequence (Register 0x0E10 to
Register 0x0E3F) .......................................................................... 98
Rev. G | Page 2 of 106
Data Sheet
Applications Information ............................................................ 102
Power Supply Partitions .......................................................... 102
Thermal Performance.............................................................. 102
AD9547
Calculating the Digital Filter Coefficients .............................103
Outline Dimensions ......................................................................106
Ordering Guide .........................................................................106
REVISION HISTORY
11/14—Rev. F to Rev. G
Changes to Figure 3 Caption to Figure 6 Caption ......................18
Changes to Figure 7 Caption, Figure 8 Caption, Figure 10
Caption, and Figure 11 Caption ....................................................19
5/14—Rev. E to Rev. F
Changes to Table 21 ........................................................................15
Added Figure 32: Renumbered Sequentially ...............................23
Changes to Frequency Tuning Word History Section ...............36
Added Disabling Accidental Automatic EEPROM Download
Section ..............................................................................................48
Changes to Buffered/Active Registers Section ............................59
Changes to Register Map Section, and Opt Column,
Table 37 .............................................................................................60
Changes to Table 66 ........................................................................76
12/13—Rev. D to Rev. E
Changes to Calculating Digital Filter Coefficients Section .....101
Changes to Calculation of the α Register Values Section ........102
6/13—Rev. C to Rev. D
Change to Table 16 ..........................................................................10
Changes to IRQ Pin Section ..........................................................45
Changes to Programming the EEPROM to Include a Clock
Part ID Section ................................................................................49
Changes to Bit 0, Table 121 ............................................................89
Changes to Status Readback (Register 0x0D00 to
Register 0x0D19) Section ...............................................................93
2/13—Rev. B to Rev. C
Change to Pin 38, Description Column, Table 21 ......................16
Added Figure 31, Renumbered Sequentially ...............................23
Changes to Automatic Priority-Based Reference Switchover
Section; Added Table 23, Renumbered Sequentially ......................30
Changes to Low Loop Bandwidth Applications Using a
TCXO/OCXO Section ....................................................................37
Changes to EEPROM Upload Section and EEPROM
Download Section ...........................................................................47
Added Programming the EEPROM to Include a Clock
Part ID Section ................................................................................49
Changes to Read Section ................................................................51
Added Figure 54 .............................................................................. 53
Changes to t
C
Parameter, Description Column, Table 34 .......... 54
Changes to Table 37 ........................................................................ 59
Added User Scratch Pad (Eight Bytes), Address 0x0C00 to
Address 0x0C07, Table 37 .............................................................. 66
Changes to Table 40 ........................................................................ 68
Added Clock Part Serial ID (Register 0x0C00 to
Register 0x0C07) Section and Table 133 ...................................... 92
Changes to Table 146, Description Column................................ 96
Changes to Table 147, Description Column................................ 97
Added Table 158 and Table 159..................................................... 99
11/10—Rev. A to Rev. B
Changes to Pulse Width High, t
HIGH
Parameter, Table 17 and
SCLK to Valid SDIO and SDO, t
DV
Parameter, Table 17 ............ 11
Changes to Addr 0x0002, Def Column, Table 36 and Addr
0x0003, Def Column, Table 36 ...................................................... 58
Changes to Addr 0x0632, Table 36 ............................................... 61
Changes to Addr 0x0680, Table 36 ............................................... 62
Changes to Addr 0x06B2, Table 36 ............................................... 63
Changes to Address 0x0002, Description, Table 39.................... 67
Changes to Bit 7 and Bit 6, Table 78 ............................................. 78
Changes to Address 0x629 and Address 0x62A, Table 87, and
Bit 7 and Bit 6, Table 88 .................................................................. 80
Changes to Address 0x65B and Address 0x65C, Table 97, and
Bit 7 and Bit 6, Table 98 .................................................................. 82
Changes to Address 0x6A9 and Address 0x6AA, Table 107 ..... 84
Changes to Bit 7 and Bit 6, Table 108 ........................................... 85
Changes to Address 0x6DB and Address 0x6DC, Table 117 .... 87
9/10—Rev. 0 to Rev. A
Change to Frequency Range (CMOS), Single-Ended Operation
Parameter, Table 8 ............................................................................. 7
Added Low Loop Bandwidth Applications Using a
TCXO/OCXO Section and Choosing the System Clock
Oscillator Frequency Section......................................................... 37
Moved System Clock Period Section ............................................ 39
7/09—Revision 0: Initial Version
Rev. G | Page 3 of 106
AD9547
SPECIFICATIONS
Data Sheet
Minimum and maximum values apply for the full range of supply voltage and operating temperature variation. Typical values apply for
AVDD3 = DVDD3 = 3.3 V, AVDD = DVDD = 1.8 V, T
A
= 25°C, I
DAC
= 20 mA (full scale), unless otherwise noted.
SUPPLY VOLTAGE
Table 1.
Parameter
DVDD3
DVDD
AVDD3
3.3 V Supply (Typical)
1.8 V Supply (Alternative)
AVDD
Min
3.135
1.71
3.135
3.135
1.71
1.71
Typ
3.30
1.80
3.30
3.30
1.80
1.80
Max
3.465
1.89
3.465
3.465
1.89
1.89
Unit
V
V
V
V
V
V
Test Conditions/Comments
Pin 7, Pin 58
Pin 1, Pin 6, Pin 8, Pin 10, Pin 11, Pin 53, Pin 59, Pin 64
Pin 16, Pin 33, Pin 43, Pin 49
Pin 25, Pin 31
Pin 25, Pin 31
Pin 17, Pin 18, Pin 23, Pin 28, Pin 32, Pin 36, Pin 39, Pin 42, Pin 46, Pin 50
SUPPLY CURRENT
The test conditions for the maximum supply current are the same as the test conditions for the All Blocks Running section of Table 3. The
test conditions for the typical supply current are the same as the test conditions for the Typical Configuration section of Table 3.
Table 2.
Parameter
I
DVDD3
I
DVDD
I
AVDD3
3.3 V Supply (Typical)
1.8 V Supply (Alternative)
I
AVDD
Min
Typ
1.5
190
52
24
24
135
Max
3
215
70
55
55
150
Unit
mA
mA
mA
mA
mA
mA
Test Conditions/Comments
Pin 7, Pin 58
Pin 1, Pin 6, Pin 8, Pin 10, Pin 11, Pin 53, Pin 59, Pin 64
Pin 16, Pin 33, Pin 43, Pin 49
Pin 25, Pin 31
Pin 25, Pin 31
Pin 17, Pin 18, Pin 23, Pin 28, Pin 32, Pin 36, Pin 39, Pin 42, Pin 46, Pin 50
POWER DISSIPATION
Table 3.
Parameter
TYPICAL CONFIGURATION
Min
Typ
800
Max
1100
Unit
mW
Test Conditions/Comments
f
SYSCLK
= 20 MHz
1
; f
S
= 1 GHz
2
; f
DDS
= 122.88 MHz
3
; one LVPECL clock
distribution output running at 122.88 MHz (all others powered
down); one input reference running at 100 MHz (all others
powered down)
f
SYSCLK
= 20 MHz
1
; f
S
= 1 GHz
2
; f
DDS
= 399 MHz
3
; all clock distribution
outputs configured as LVPECL at 399 MHz; all input references
configured as differential at 100 MHz; fractional-N active (R = 10,
S = 39, U = 9, V = 10)
Conditions = typical configuration; no external pull-up or
pull-down resistors
Conditions = typical configuration; table values show the change
in power due to the indicated operation
f
SYSCLK
= 1 GHz
1
; high frequency direct input mode
ALL BLOCKS RUNNING
900
1250
mW
FULL POWER-DOWN
INCREMENTAL POWER DISSIPATION
SYSCLK PLL Off
Input Reference On
Differential
Single-Ended
Output Distribution Driver On
LVDS
LVPECL
CMOS
1
2
13
mW
−105
7
13
70
75
65
mW
mW
mW
mW
mW
mW
Single 3.3 V CMOS output with a 10 pF load
f
SYSCLK
is the frequency at the SYSCLKP and SYSCLKN pins.
f
S
is the sample rate of the output DAC.
3
f
DDS
is the output frequency of the DDS.
Rev. G | Page 4 of 106
Data Sheet
LOGIC INPUTS (M0 TO M7, RESET)
Table 4.
Parameter
INPUT VOLTAGE
Input High Voltage (V
IH
)
Input Low Voltage (V
IL
)
INPUT CURRENT (I
INH
, I
INL
)
INPUT CAPACITANCE (C
IN
)
Min
2.1
±80
3
0.8
±200
Typ
Max
Unit
V
V
µA
pF
Test Conditions/Comments
AD9547
LOGIC OUTPUTS (M0 TO M7, IRQ)
Table 5.
Parameter
OUTPUT VOLTAGE
Output High Voltage (V
OH
)
Output Low Voltage (V
OL
)
IRQ LEAKAGE CURRENT
Active Low Output Mode
Active High Output Mode
Min
2.7
0.4
1
1
Typ
Max
Unit
V
V
µA
µA
Test Conditions/Comments
I
OH
= 1 mA
I
OL
= 1 mA
Open-drain mode
V
OH
= 3.3 V
V
OL
= 0 V
SYSTEM CLOCK INPUTS (SYSCLKP, SYSCLKN)
Table 6.
Parameter
SYSTEM CLOCK PLL BYPASSED
Input Frequency Range
Minimum Input Slew Rate
Duty Cycle
Common-Mode Voltage
Differential Input Voltage Sensitivity
Min
500
1000
40
1.2
100
Typ
Max
1000
60
Unit
MHz
V/µs
%
V
mV p-p
Test Conditions/Comments
Minimum limit imposed for jitter performance
Internally generated
Minimum voltage across pins is required to ensure
switching between logic states; the instantaneous
voltage on either pin must not exceed the supply rails;
ac ground the unused input to accommodate
single-ended operation
Single-ended, each pin
Input Capacitance
Input Resistance
SYSTEM CLOCK PLL ENABLED
PLL Output Frequency Range
Phase Frequency Detector (PFD) Rate
Frequency Multiplication Range
VCO Gain
High Frequency Path
Input Frequency Range
Minimum Input Slew Rate
Frequency Divider Range
Common-Mode Voltage
Differential Input Voltage Sensitivity
2
2.5
900
6
70
100.1
200
1
1
100
500
8
1000
150
255
pF
kΩ
MHz
MHz
Assumes valid system clock and PFD rates
MHz/V
MHz
V/µs
V
mV p-p
Input Capacitance
Input Resistance
3
2.5
pF
kΩ
Minimum limit imposed for jitter performance
Binary steps (M = 1, 2, 4, 8)
Internally generated
This is the minimum voltage required across the pins to
ensure switching between logic states; the
instantaneous voltage on either pin must not exceed
the supply rails; ac ground the unused input to
accommodate single-ended operation
Single-ended, each pin
Rev. G | Page 5 of 106
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