S25FL064L
64-Mbit (8-Mbyte)
3.0 V FL-L SPI Flash Memory
General Description
The Cypress FL-L Family devices are Flash Nonvolatile Memory products using:
Floating Gate technology
65-nm process lithography
The FL-L family connects to a host system via a Serial Peripheral Interface (SPI). Traditional SPI single bit serial input and output
(Single I/O or SIO) is supported as well as optional two bit (Dual I/O or DIO) and four bit wide Quad I/O (QIO), and Quad Peripheral
Interface (QPI) commands. In addition, there are Double Data Rate (DDR) read commands for QIO and QPI that transfer address
and read data on both edges of the clock.
The architecture features a Page Programming Buffer that allows up to 256-bytes to be programmed in one operation and provides
individual 4 KB sector, 32 KB half block sector, 64 KB block sector, or entire chip erase.
By using FL-L family devices at the higher clock rates supported, with Quad commands, the instruction read transfer rate can match
or exceed traditional parallel interface, asynchronous, NOR Flash memories, while reducing signal count dramatically.
The FL-L family products offer high densities coupled with the flexibility and fast performance required by a variety of mobile or
embedded applications. Provides an ideal storage solution for systems with limited space, signal connections, and power. These
memories offer flexibility and performance well beyond ordinary serial flash devices. They are ideal for code shadowing to RAM,
executing code directly (XIP), and storing re-programmable data.
Features
Serial Peripheral Interface (SPI) with Multi-I/O
– Clock polarity and phase modes 0 and 3
– Double Data Rate (DDR) option
– Quad peripheral interface (QPI) option
– Extended addressing: 24- or 32-bit address options
– Serial command subset and footprint compatible with S25FL-A,
S25FL1-K, S25FL-P, S25FL-S, and S25FS-S SPI families
– Multi I/O command subset and footprint compatible with S25FL-P,
S25FL-S and S25FS-S SPI families
Read
– Commands: Normal, Fast, Dual I/O, Quad I/O, DualO, QuadO,
DDR Quad I/O
– Modes: Burst wrap, Continuous (XIP), QPI
– Serial flash discoverable parameters (SFDP) for configuration
information
Program Architecture
– 256-Bytes page programming buffer
– Program suspend and resume
Erase Architecture
– Uniform 4 KB sector erase
– Uniform 32 KB half block erase
– Uniform 64 KB block erase
– Chip erase
– Erase suspend and resume
100,000 Program-Erase Cycles, minimum
20 Year Data Retention, minimum
Security Features
– Status and configuration Register protection
– Four security regions of 256-bytes each outside the main Flash
array
– Legacy block protection: Block range
– Individual and region protection
– Individual block lock: Volatile individual sector/block
– Pointer region: Nonvolatile sector/block range
– Power supply Lock-down, password, or permanent protection
of security regions 2 and 3 and pointer region
Technology
– 65-nm Floating Gate technology
Single Supply Voltage with CMOS I/O
– 2.7 V to 3.6 V
Temperature Range / Grade
– Industrial (–40°C to +85°C)
– Industrial Plus (–40°C to +105°C)
– Automotive, AEC-Q100 Grade 3 (–40°C to +85°C)
– Automotive, AEC-Q100 Grade 2 (–40°C to +105°C)
– Automotive, AEC-Q100 Grade 1 (–40°C to +125°C)
Packages (All Pb-free)
– 8-lead SOIC 208 mil (SOC008)
– 16-lead SOIC 300 mil (SO3016)
– USON 4
4 mm (UNF008)
– WSON 5 x 6 mm (WND008)
– BGA-24 6
8 mm
– 5
5 ball (FAB024) footprint
– 4
6 ball (FAC024) footprint
– Known good die and known tested die
Cypress Semiconductor Corporation
Document Number: 002-12878 Rev. *E
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised July 11, 2018
S25FL064L
Performance Summary
Maximum Read Rates SDR
Command
Read
Fast Read
Dual Read
Quad Read
Clock Rate (MHz)
50
108
108
108
MBps
6.25
13.5
27
54
Maximum Read Rates DDR
Command
DDR Quad Read
Clock Rate (MHz)
54
MBps
54
Typical Program and Erase Rates
Operation
Page Programming
4 KBytes Sector Erase
32 KBytes Half Block Erase
64 KBytes Block Erase
KBytes/s
569
61
106
142
Typical Current Consumption
Operation
Read 50 MHz
Fast Read 5MHz
Fast Read 10 MHz
Fast Read 20 MHz
Fast Read 50 MHz
Fast Read 108 MHz
Quad I/O / QPI Read 108 MHz
Quad I/O / QPI DDR Read 33MHz
Quad I/O / QPI DDR Read 54MHz
Program
Erase
Standby SPI
Standby QPI
Deep Power Down
Typical Current
10
10
10
10
15
25
25
15
30
40
40
20
60
2
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
µA
µA
µA
Document Number: 002-12878 Rev. *E
Page 2 of 152
S25FL064L
Contents
1.
1.1
2.
2.1
2.2
2.3
2.4
3.
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
3.10
3.11
3.12
3.13
3.14
4.
4.1
5.
5.1
5.2
5.3
5.4
6.
6.1
6.2
6.3
6.4
6.5
6.6
7.
7.1
7.2
7.3
7.4
7.5
7.6
7.7
8.
8.1
8.2
8.3
8.4
8.5
Product Overview
........................................................ 4
Migration Notes.............................................................. 4
Connection Diagrams..................................................
SOIC 16-Lead ................................................................
8 Connector Packages...................................................
BGA Ball Footprint .........................................................
Special Handling Instructions for FBGA Packages........
6
6
6
8
8
8.6
8.7
8.8
8.9
8.10
8.11
8.12
9.
9.1
9.2
Erase Flash Array Commands...................................... 91
Security Regions Array Commands.............................. 97
Individual Block Lock Commands ................................. 99
Pointer Region Command........................................... 103
Individual and Region Protection (IRP) Commands ... 104
Reset Commands ....................................................... 109
Deep Power Down Commands................................... 110
Data Integrity
............................................................. 113
Erase Endurance ........................................................ 113
Data Retention ............................................................ 113
Signal Descriptions
..................................................... 9
Input/Output Summary................................................... 9
Multiple Input / Output (MIO)........................................ 10
Serial Clock (SCK) ....................................................... 10
Chip Select (CS#) ........................................................ 10
Serial Input (SI) / IO0 ................................................... 10
Serial Output (SO) / IO1............................................... 10
Write Protect (WP#) / IO2 ............................................ 10
IO3 / RESET# .............................................................. 11
RESET# ....................................................................... 11
Voltage Supply (VCC).................................................. 11
Supply and Signal Ground (V
SS
) ................................. 11
Not Connected (NC) .................................................... 11
Reserved for Future Use (RFU)................................... 12
Do Not Use (DNU) ....................................................... 12
Block Diagram............................................................
13
System Block Diagrams............................................... 13
Signal Protocols.........................................................
SPI Clock Modes .........................................................
Command Protocol ......................................................
Interface States............................................................
Data Protection ............................................................
16
16
17
22
26
10. Software Interface Reference
.................................. 114
10.1 JEDEC JESD216B Serial Flash Discoverable
Parameters ................................................................. 114
10.2 Device ID Address Map .............................................. 122
10.3 Initial Delivery State .................................................... 122
11.
11.1
11.2
11.3
11.4
11.5
11.6
12.
12.1
12.2
12.3
12.4
12.5
12.6
13.
14.
14.1
14.2
14.3
14.4
14.5
14.6
15.
15.1
15.2
15.3
15.4
Electrical Specifications...........................................
123
Absolute Maximum Ratings ........................................ 123
Latchup Characteristics .............................................. 123
Thermal Resistance .................................................... 123
Operating Ranges....................................................... 123
Power-Up and Power-Down ....................................... 124
DC Characteristics ...................................................... 127
Timing Specifications...............................................
130
Key to Switching Waveforms ...................................... 130
AC Test Conditions ..................................................... 130
Reset .......................................................................... 131
SDR AC Characteristics.............................................. 134
DDR AC Characteristics ............................................. 137
Embedded Algorithm Performance Tables ................. 139
Ordering Information
................................................ 140
Physical Diagrams
.................................................... 142
SOIC 8-Lead, 208 mil Body Width (SOC008)............. 142
SOIC 16-Lead, 300 mil Body Width (SO3016) ........... 143
USON 4 x 4 mm (UNF008) ......................................... 144
WSON 5x 6mm (WND008) ......................................... 145
Ball Grid Array, 24-ball 6 x 8 mm (FAB024)................ 146
Ball Grid Array, 24-ball 6 x 8 mm (FAC024) ............... 147
Other Resources
....................................................... 148
Glossary...................................................................... 148
Link to Cypress Flash Roadmap................................. 149
Link to Software .......................................................... 149
Link to Application Notes ............................................ 149
Address Space Maps.................................................
27
Overview ...................................................................... 27
Flash Memory Array..................................................... 27
ID Address Space ........................................................ 27
JEDEC JESD216 Serial Flash Discoverable Parameters
(SFDP) Space.............................................................. 28
Security Regions Address Space ................................ 28
Registers...................................................................... 28
Data Protection
..........................................................
Security Regions..........................................................
Deep Power Down .......................................................
Write Enable Commands .............................................
Write Protect Signal .....................................................
Status Register Protect (SRP1, SRP0)........................
Array Protection ...........................................................
Individual and Region Protection .................................
Commands
.................................................................
Command Set Summary..............................................
Identification Commands .............................................
Register Access Commands........................................
Read Memory Array Commands .................................
Program Flash Array Commands ................................
45
45
45
46
46
46
48
53
58
58
64
67
80
89
16. Document History
..................................................... 150
Sales, Solutions, and Legal Information ........................ 152
Worldwide Sales and Design Support ......................... 152
Products ...................................................................... 152
PSoC® Solutions ........................................................ 152
Cypress Developer Community ................................... 152
Technical Support ....................................................... 152
Document Number: 002-12878 Rev. *E
Page 3 of 152
S25FL064L
1. Product Overview
1.1
1.1.1
Migration Notes
Features Comparison
The FL064L family is command subset and footprint compatible with prior generation FL-S, FL1-K and FL-P families.
Table 1. Cypress SPI Families Comparison
Parameter
Technology Node
Architecture
Release Date
Density
Bus Width
Supply Voltage
Normal Read Speed
Fast Read Speed
Dual Read Speed
Quad Read Speed
Quad Read Speed (DDR)
Program Buffer Size
Erase Sector/Block Size
Parameter Sector Size
Sector / Block Erase Rate (typ.)
FL-L
65nm
Floating Gate
In Production
64Mb
x1, x2, x4
2.7 V - 3.6 V
6MB/s (50MHz)
13MB/s (108MHz)
26MB/s (108MHz)
52MB/s (108MHz)
54MB/s (54MHz)
256B
4KB / 32KB / 64KB
-
61 KB/s (4KB)
106 KB/s (32KB
142KB/s (64KB)
Page Programming Rate (typ.)
Security Region / OTP
Individual and Region Protection
or Advanced Sector Protection
Erase Suspend/Resume
Program Suspend/Resume
Operating Temperature
569 KB/s (256B)
1024B
Yes
Yes
Yes
–40°C to +85°C
–40°C to +105°C
–40°C to +125°C
Note:
1. Refer to individual data sheets for further details
FL-L
65nm
Floating Gate
In Production
256Mb
x1, x2, x4
2.7 V - 3.6 V
6MB/s (50MHz)
16.5MB/s (133MHz)
33MB/s (133MHz)
66MB/s (133MHz)
66MB/s (66MHz)
256B
4KB / 32KB / 64KB
-
80 KB/s (4KB)
168 KB/s (32KB
237KB/s (64KB)
854KB/s (256B)
1024B
Yes
Yes
Yes
–40°C to +85°C
–40°C to +105°C
–40°C to +125°C
1.2 MB/s (256B)
1.5 MB/s (512B)
1024B
Yes
Yes
Yes
–40°C to +85°C
–40°C to +105°C
500 KB/s
FL-S
65nm
MirrorBit Eclipse™
In Production
128Mb - 1Gb
x1, x2, x4
2.7 V - 3.6 V / 1.65 V - 3.6 V
V
IO
6MB/s (50MHz)
17MB/s (133MHz)
26MB/s (104MHz)
52MB/s (104MHz)
80MB/s (80MHz)
256B / 512B
64KB / 256KB
4KB (option)
80 KB/s (4KB)
128 KB/s (64KB)
365 KB/s
768B (3
256B)
Yes
Yes
Yes
–40°C to +85°C
–40°C to +105°C
–40°C to +125°C
256B
4KB / 64KB
256B
64KB / 256KB
4KB
130 KB/s
®
FL1-K
90nm
Floating Gate
In Production
16Mb - 64Mb
x1, x2, x4
2.7 V - 3.6 V
6MB/s (50MHz)
13MB/s (108MHz)
26MB/s (108MHz)
52MB/s (108MHz)
FL-P
90nm
MirrorBit
®
In Production
32Mb - 256Mb
x1, x2, x4
2.7 V - 3.6 V
5MB/s (40MHz)
13MB/s (104MHz)
20MB/s (80MHz)
40MB/s (80MHz)
170 KB/s
506B
No
No
No
–40°C to +85°C
–40°C to +105°C
Document Number: 002-12878 Rev. *E
Page 4 of 152
S25FL064L
1.1.2
1.1.2.1
Known Differences from Prior Generations
Error Reporting
FL-K, FL1-K and FL-P memories either do not have error status bits or do not set them if program or erase is attempted on a
protected sector. This product family does have error reporting status bits for program and erase operations. These can be set when
there is an internal failure to program or erase, or when there is an attempt to program or erase a protected sector. In these cases
the program or erase operation did not complete as requested by the command. The P_ERR or E_ERR bits and the WIP bit will be
set to and remain 1 in SR1V. The clear status register command must be sent to clear the errors and return the device to standby
state.
1.1.2.2
Status Register Protect 1 Bit
The Configuration Register 1 SRP1 Bit CR1V[0], locks the state of the Legacy Block Protection bits (SR1NV[5:2] & SR1V[5:2]),
CMP_NV (CR1NV[6]) and TBPROT_NV bit (SR1NV[6]), as Freeze did in prior generations. In the FS-S and FL-S families the
Freeze Bit also locks the state of the Configuration Register 1 BPNV_O bit (CR1NV[3]), and the Secure Silicon Region (OTP) area.
1.1.2.3
WRR Single Register Write
In some legacy SPI devices, a Write Registers (WRR) command with only one data byte would update Status Register 1 and clear
some bits in Configuration Register 1, including the Quad mode bit. This could result in unintended exit from Quad mode. This
product family only updates Status Register 1 when a single data byte is provided. The Configuration Register 1 is not modified in
this case.
1.1.2.4
Other Legacy Commands Not Supported
Autoboot Related Commands
Bank Address Related Commands
Hold# replaced by the Reset#
1.1.2.5
New Features
This product family introduces new features to Cypress SPI category memories:
Security Regions Password Protection
.
IRP Individual Region Protection
Document Number: 002-12878 Rev. *E
Page 5 of 152
stm32/stm8
京公网安备 11010802033920号
EEWORLD
