RMLV0408E Series
4Mb Advanced LPSRAM (512-kword × 8-bit)
R10DS0206EJ0200
Rev.2.00
2016.1.12
Description
The RMLV0408E Series is a family of 4-Mbit static RAMs organized 524,288-word × 8-bit, fabricated by Renesas’s
high-performance Advanced LPSRAM technologies. The RMLV0408E Series has realized higher density, higher
performance and low power consumption. The RMLV0408E Series offers low power standby power dissipation;
therefore, it is suitable for battery backup systems. It is offered in 32-pin SOP, 32-pin TSOP (II) or 32-pin sTSOP.
Features
Single 3V supply: 2.7V to 3.6V
Access time: 45ns (max.)
Current consumption:
──
Standby: 0.4µA (typ.)
Equal access and cycle times
Common data input and output
──
Three state output
Directly TTL compatible
──
All inputs and outputs
Battery backup operation
Orderable part number information
Orderable part number
Access
time
Temperature
range
Package
Shipping container
Tray
8mm×13.4mm 32-pin
plastic sTSOP
Embossed tape
RMLV0408EGSA-4S2#AA
*
RMLV0408EGSA-4S2#KA
*
RMLV0408EGSB-4S2#AA
*
45 ns
RMLV0408EGSB-4S2#HA
*
-40 ~ +85°C
Tray
400-mil 32pin
plastic TSOP (II)
Embossed tape
RMLV0408EGSP-4S2#CA
*
Tube
525-mil 32-pin
plastic SOP
Embossed tape
RMLV0408EGSP-4S2#HA
*
R10DS0206EJ0200 Rev.2.00
2016.1.12
Page 1 of 10
RMLV0408E Series
Pin Arrangement
32-pin SOP
32-pin TSOP (II)
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Vcc
A15
A17
WE#
A13
A8
A9
A11
OE#
A10
CS#
I/O7
I/O6
I/O5
I/O4
I/O3
A11
A9
A8
A13
WE#
A18
A15
Vcc
A17
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32-pin sTSOP
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE#
A10
CS#
I/O7
I/O6
I/O5
I/O4
I/O3
Vss
I/O2
I/O1
I/O0
A0
A1
A2
A3
(Top view)
(Top view)
Pin Description
Pin name
V
CC
V
SS
A0 to A18
I/O0 to I/O7
CS#
WE#
OE#
Power supply
Ground
Address input
Data input/output
Chip select
Write enable
Output enable
Function
R10DS0206EJ0200 Rev.2.00
2016.1.12
Page 2 of 10
RMLV0408E Series
Block Diagram
A0
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
V
CC
V
SS
Row
Decoder
・
・
・
・
・
Memory Matrix
2,048 x 2,048
I/O0
Input
Data
Control
・
・
Column I/O
Column Decoder
・
・
I/O7
A1 A2 A3 A14 A15 A16 A17 A18
・
・
CS#
WE#
OE#
Timing Pulse Generator
Read/Write Control
Operation Table
CS#
H
L
L
L
Note 1.
WE#
X
H
L
H
H: V
IH
L:V
IL
OE#
X
L
X
H
X: V
IH
or V
IL
I/O0 to I/O7
High-Z
Dout
Din
High-Z
Operation
Standby
Read
Write
Output disable
Absolute Maximum Ratings
Parameter
Power supply voltage relative to V
SS
Terminal voltage on any pin relative to V
SS
Power dissipation
Operation temperature
Symbol
V
CC
V
T
P
T
Topr
Value
-0.5 to +4.6
-0.5
*2
to V
CC
+0.3
*3
0.7
-40 to +85
-65 to +150
-40 to +85
unit
V
V
W
°C
°C
°C
Storage temperature range
Tstg
Storage temperature range under bias
Tbias
Note 2. -3.0V for pulse
≤
30ns (full width at half maximum)
3. Maximum voltage is +4.6V.
R10DS0206EJ0200 Rev.2.00
2016.1.12
Page 3 of 10
RMLV0408E Series
DC Operating Conditions
Symbol
Supply voltage
V
CC
V
SS
Input high voltage
V
IH
Input low voltage
V
IL
Ambient temperature range
Ta
Note 4. -3.0V for pulse
≤
30ns (full width at half maximum)
Parameter
Min.
2.7
0
2.2
-0.3
-40
Typ.
3.0
0
─
─
─
Max.
3.6
0
V
CC
+0.3
0.6
+85
Unit
V
V
V
V
°C
Note
4
DC Characteristics
Parameter
Input leakage current
Output leakage current
Operating current
Average operating current
I
CC1
─
I
CC2
Standby current
Standby current
I
SB
─
─
─
─
I
SB1
─
─
Output high voltage
V
OH
V
OH2
Output low voltage
V
OL
V
OL2
Note
2.4
V
CC
-0.2
─
─
─
─
─
─
─
─
5
7
─
─
0.4
0.2
A
A
V
V
V
V
~+70°C
~+85°C
I
OH
= -1mA
I
OH
= -0.1mA
I
OL
= 2.1mA
I
OL
= 0.1mA
─
─
0.1
*5
0.4
*5
─
25
2.5
0.3
2
3
mA
mA
mA
A
A
Symbol
| I
LI
|
| I
LO
|
I
CC
Min.
─
─
─
─
Typ.
─
─
─
─
Max.
1
1
10
20
Unit
A
A
mA
mA
Test conditions
Vin = V
SS
to V
CC
CS# = V
IH
or OE# =V
IH
or WE#= V
IL
,
V
I/O
= V
SS
to V
CC
CS# =V
IL
,
Others = V
IH
/V
IL
, I
I/O
= 0mA
Cycle = 55ns, duty = 100%, I
I/O
= 0mA,
CS# = V
IL
, Others = V
IH
/V
IL
Cycle = 45ns, duty = 100%, I
I/O
= 0mA,
CS# = V
IL
, Others = V
IH
/V
IL
Cycle = 1s, duty = 100%, I
I/O
= 0mA,
CS#
≤
0.2V, V
IH
≥
Vcc-0.2V, V
IL
≤
0.2V
CS# =V
IH
,
Others = V
SS
to V
CC
~+25°C
~+40°C
Vin = V
SS
to V
CC
,
CS#
≥
V
CC
-0.2V
5. Typical parameter indicates the value for the center of distribution at 3.0V (Ta=25ºC), and not 100% tested.
Capacitance
(Vcc = 2.7V ~ 3.6V, f = 1MHz, Ta = -40 ~ +85°C)
Parameter
Symbol
Min.
Input capacitance
C in
─
Input / output capacitance
C
I/O
─
Note 6. This parameter is sampled and not 100% tested.
Typ.
─
─
Max.
8
10
Unit
pF
pF
Test conditions
Vin =0V
V
I/O
=0V
Note
6
6
R10DS0206EJ0200 Rev.2.00
2016.1.12
Page 4 of 10
RMLV0408E Series
AC Characteristics
Test Conditions (Vcc = 2.7V ~ 3.6V, Ta = -40 ~ +85°C)
Input pulse levels: V
IL
= 0.4V, V
IH
= 2.4V
Input rise and fall time: 5ns
Input and output timing reference level: 1.4V
Output load: See figures (Including scope and jig)
I/O
C
L
= 30 pF
1.4V
R
L
= 500
ohm
Read Cycle
Parameter
Read cycle time
Address access time
Chip select access time
Output enable to output valid
Output hold from address change
Chip select to output in low-Z
Output enable to output in low-Z
Chip deselect to output in high-Z
Output disable to output in high-Z
Symbol
t
RC
t
AA
t
ACS
t
OE
t
OH
t
CLZ
t
OLZ
t
CHZ
t
OHZ
Min.
45
─
─
─
10
10
5
0
0
Max.
─
45
45
22
─
─
─
18
18
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
7,8
7,8
7,8,9
7,8,9
Note
Write Cycle
Parameter
Symbol
Min.
Max.
Unit
Note
Write cycle time
t
WC
45
─
ns
Address valid to write end
t
AW
35
─
ns
Chip select to write end
t
CW
35
─
ns
Write pulse width
t
WP
35
─
ns
10
Address setup time to write start
t
AS
0
─
ns
Write recovery time from write end
t
WR
0
─
ns
Data to write time overlap
t
DW
25
─
ns
Data hold from write end
t
DH
0
─
ns
Output enable from write end
t
OW
5
─
ns
7
Output disable to output in high-Z
t
OHZ
0
18
ns
7,9
Write to output in high-Z
t
WHZ
0
18
ns
7,9
Note 7. This parameter is sampled and not 100% tested.
8. At any given temperature and voltage condition, t
CHZ
max is less than t
CLZ
min, and t
OHZ
max is less than t
OLZ
min, for any device.
9. t
CHZ
, t
OHZ
and t
WHZ
are defined as the time when the I/O pins enter a high-impedance state and are not
referred to the I/O levels.
10. t
WP
is the interval between write start and write end.
A write starts when both of CS# and WE# become active
A write is performed during the overlap of a low CS#, a low WE#
A write ends when any of CS#, WE# becomes inactive.
R10DS0206EJ0200 Rev.2.00
2016.1.12
Page 5 of 10
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