AD9954/PCBZ datasheet, PDF - EEWORLD Datasheet

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AD9954/PCBZ: DescriptionData conversion IC development tool AD9954 Eval Brd; CategoryEmbedded solution Engineering tools Analog and digital IC development tools Data conversion IC development tools; File Size732KB，41 Pages; ManufacturerADI; Websitehttps://www.analog.com; Environmental Compliance

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AD9954/PCBZ Overview

Data conversion IC development tool AD9954 Eval Brd

AD9954/PCBZ Parametric

Parameter Name	Attribute value
Maker	ADI
Product Category	Data conversion IC development tools
product	Evaluation Boards
type	DAC
Tools for assessment	AD9954
Working power voltage	1.8 V, 3.3 V
Encapsulation	Bulk
Description/Function	Direct digital synthesizer DAC output evaluation board
series	AD9954
Interface Type	Serial
Maximum operating temperature	+ 105 C
Minimum operating temperature	- 40 C
Factory packaging quantity	1
unit weight	295.288 g

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Data Sheet

FEATURES

400 MSPS internal clock speed

Integrated 14-bit DAC

Programmable phase/amplitude dithering

32-bit frequency tuning accuracy

14-bit phase tuning accuracy

Phase noise better than –120 dBc/Hz

Excellent dynamic performance

>80 dB narrowband SFDR

Serial input/output (I/O) control

Ultrahigh speed analog comparator

Automatic linear and nonlinear frequency sweeping

4 frequency/phase offset profiles

1.8 V power supply

Software and hardware controlled power-down

48-lead TQFP

Integrated 1024 word × 32-bit RAM

PLL-based REFCLK multiplier

Internal oscillator, can be driven by a single crystal

Phase modulation capability

Multichip synchronization

400 MSPS, 14-Bit, 1.8 V CMOS,

Direct Digital Synthesizer

AD9954

GENERAL DESCRIPTION

The AD9954 is a direct digital synthesizer (DDS) that uses

advanced technology, coupled with an internal high speed, high

performance DAC to form a complete, digitally programmable,

high frequency synthesizer capable of generating a frequency-

agile analog output sinusoidal waveform at up to 160 MHz.

The AD9954 enables fast frequency hopping coupled with fine

tuning of both frequency (0.01 Hz or better) and phase (0.022°

granularity).

The AD9954 is programmed via a high speed serial I/O port.

The device includes static RAM to support flexible frequency

sweep capability in several modes, plus a user-defined linear

sweep mode of operation. Also included is an on-chip high

speed comparator for applications requiring a square wave

output. An on-chip oscillator and PLL circuitry provide users

with multiple approaches to generate the device’s system clock.

The AD9954 is specified to operate over the extended industrial

temperature range (see Table 2).

APPLICATIONS

Agile LO frequency synthesis

Programmable clock generators

FM chirp source for radar and scanning systems

Automotive radars

Test and measurement equipment

Acousto-optic device drivers

BASIC BLOCK DIAGRAM

AD9954

400MSPS

DDS CORE

14-BIT

DAC

DIGITAL

SINE

WAVE

COMPARATOR

REF CLOCK

INPUT CIRCUITRY

TIMING AND

CONTROL

USER INTERFACE

Figure 1.

Rev. C

Document Feedback

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Technical Support

www.analog.com

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

03374-038

AD9954

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

General Description ......................................................................... 1

Basic Block Diagram ........................................................................ 1

Revision History ............................................................................... 2

Functional Block Diagram .............................................................. 3

Electrical Specifications ................................................................... 4

Absolute Maximum Ratings ............................................................ 7

Explanation of Test Levels ........................................................... 7

ESD Caution .................................................................................. 7

Pin Configuration and Function Descriptions ............................. 8

Typical Performance Characteristics ........................................... 10

Theory of Operation ...................................................................... 13

Component Blocks ..................................................................... 13

Modes of Operation ................................................................... 16

Synchronization—Register Updates (I/O UPDATE) ............ 21

Serial Port Operation ................................................................. 23

Data Sheet

Serial Interface Port Pin Descriptions ..................................... 24

MSB/LSB Transfers .................................................................... 24

RAM I/O via Serial Port ............................................................ 24

Instruction Byte .......................................................................... 25

Control Register Bit Descriptions ............................................ 29

Other Register Descriptions ..................................................... 31

Layout Considerations ............................................................... 32

Detailed Programming Examples ................................................ 33

Single-Tone Mode ...................................................................... 33

Linear Sweep Mode .................................................................... 33

RAM Mode.................................................................................. 33

Suggested Application Circuits ..................................................... 35

Evaluation Board Schematics........................................................ 36

Outline Dimensions ....................................................................... 39

Ordering Guide .......................................................................... 39

REVISION HISTORY

2/2017—Rev.

B to Rev. C

Changes to Features Section............................................................ 1

5/2009—Rev. A to Rev. B

Changes to Figure 29 and Figure 30............................................. 24

Changes to Table 12 ........................................................................ 26

Changes to Figure 34 ...................................................................... 35

Updated Outline Dimensions ....................................................... 39

Changes to Ordering Guide .......................................................... 39

1/2007—Rev. 0 to Rev. A

Changes to Layout .............................................................. Universal

Changes to Features, General Description, and Figure 1 ............ 1

Changes to Figure 2 .......................................................................... 3

Changes to Table 1 ............................................................................ 4

Changes to Table 4 ............................................................................ 8

Changes to Figure 5 to Figure 10 .................................................. 10

Changes to Figure 12 ...................................................................... 11

Changes to Figure 17 to Figure 18 Captions ............................... 12

Deleted Figure 19; Renumbered Sequentially............................. 12

Added Table 5; Renumbered Sequentially .................................. 13

Changes to Component Block Section and Table 6 ................... 13

Changes to Figure 20 ...................................................................... 15

Changes to Modes of Operation Section and Table 8 ............... 16

Changes to Table 9.......................................................................... 17

Changes to Synchronization; Register Updates (I/O UPDATE)

Section and Figure 24..................................................................... 21

Changes to Serial Port Operation Section .................................. 23

Changes to Serial Interface Port Pin Description Section,

MSB/LSB Transfers Section, and RAM I/O Via Serial Port

Section .............................................................................................. 24

Inserted Figure 29 and Figure 30; Renumbered Sequentially .. 24

Changes to Instruction Byte Section, Register Maps and

Descriptions Section, and Table 12 .............................................. 25

Changes to Table 13 ....................................................................... 26

Changes to Table 14 ....................................................................... 28

Added Single-Tone Mode Section, Linear Sweep Mode Section,

Table 15, and RAM Mode Section ............................................... 33

Added, and Table 16 ....................................................................... 34

Inserted Figure 35........................................................................... 36

Inserted Figure 36........................................................................... 37

Inserted Figure 37........................................................................... 38

Updated Outline Dimensions ....................................................... 39

Changes to Ordering Guide .......................................................... 39

10/2003—Revision 0: Initial Version

Rev. C | Page 2 of 40

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