AS4C128M8D1-6TIN
Revision History
AS4C128M8D1-6TIN 66pin TSOP
II
PACKAGE
Revision
Rev 1.0
Details
Initial Issue
Date
Dec.
2016
Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211
Alliance Memory Inc. reserves the right to change products or specification without notice
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AS4C128M8D1-6TIN
Features
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Description
The
AS4C128M8D1-6TIN
is
a
four
bank
DDR DRAM organized as 4 banks x 32Mbit x 8. The
AS4C128M8D1-6TIN
achieves high speed data
transfer rates by employing a chip architecture that
pre-fetches multiple bits and then synchronizes
the output data to a system clock.
All of the control, address, circuits are synchronized
with the positive edge of an externally supplied clock. I/O
transactions are occurring on both edges of DQS.
Operating the four memory banks in an interleaved
fashion allows random access operation to occur at a
higher rate than is possible with standard DRAMs. A
sequential and gapless data rate is possible
depending on burst length, CAS latency and speed
grade of the device.
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High speed data transfer rates with system frequency
up to
166MHz
Data Mask for Write Control
Four Banks controlled by BA0 & BA1
Programmable CAS Latency: 2, 2.5, 3
Programmable Wrap Sequence: Sequential
or Interleave
Programmable Burst Length:
2, 4, 8 for Sequential Type
2, 4, 8 for Interleave Type
Automatic and Controlled Precharge Command
Power Down Mode
Auto Refresh and Self Refresh
Refresh Interval: 8192 cycles/64 ms
Available in 66 Pin TSOP II
SSTL-2 Compatible I/Os
Double Data Rate (DDR)
Bidirectional Data Strobe (DQS) for input and output
data, active on both edges
On-Chip DLL aligns DQ and DQs transitions with CK
transitions
Differential clock inputs CK and CK
VDD = 2.5V ± 0.2V, VDDQ = 2.5V ± 0.2V
tRAS lockout supported
Concurrent auto precharge option is supported
Table 1. Ordering Information
Part Number
AS4C128M8D1-6TIN
Org
128Mx8
Temperature
Industrial
-40°C to +85°C
MaxClock (MHz)
166
Package
66pin TSOPII
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AS4C128M8D1-6TIN
66 Pin Plastic TSOP-II
PIN CONFIGURATION
128Mb x 8
V
DD
DQ
0
V
DDQ
NC
DQ
1
V
SSQ
NC
DQ
2
V
DDQ
NC
DQ
3
V
SSQ
NC
NC
V
DDQ
NC
A
13
V
DD
NC
NC
WE
CAS
RAS
CS
NC
BA
0
BA
1
AP/A
10
A
0
A
1
A
2
A
3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
66 PIN TSOP (II)
13
(400mil x 875 mil)
14
15
Bank Address
BA
0
-BA
1
16
17
Row Address
18
A
0
-A
13
19
20
Auto Precharge
A
10
21
22
23
24
25
26
27
28
29
30
31
32
33
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
V
SS
DQ
7
V
SSQ
NC
DQ
6
V
DDQ
NC
DQ
5
V
SSQ
NC
DQ
4
V
DDQ
NC
NC
V
SSQ
DQS
NC
V
REF
V
SS
DM
CK
CK
CKE
NC
A
12
A
11
A
9
A
8
A
7
A
6
A
5
A
4
V
SS
Pin Names
CK, CK
CKE
CS
RAS
CAS
WE
DQS (UDQS, LDQS)
A
0
–A
13
BA
0
, BA
1
Differential Clock Input
Clock Enable
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Data Strobe (Bidirectional)
Address Inputs
Bank Select
V
SS
V
DDQ
V
SSQ
NC
V
REF
DQ’s
DM (UDM, LDM)
V
DD
Data Input/Output
Data Mask
Power
(+2.5V )
Ground
Power for I/O’s
(+2.5V)
Ground for I/O’s
Not connected
Reference Voltage for Inputs
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AS4C128M8D1-6TIN
Block Diagram
128M x 8
Column Addresses
A
0
- A9, A
11
, AP, BA
0
, BA
1
Row Addresses
A
0
- A
13
, BA
0
, BA
1
Column address
counter
Column address
buffer
Row address
buffer
Refresh Counter
Row decoder
Memory array
Column decoder
Sense amplifier & I(O) bus
Row decoder
Memory array
Bank 1
Row decoder
Memory array
Bank 2
Row decoder
Memory array
Bank 3
Bank 0
16384 x 2048
Column decoder
Sense amplifier & I(O) bus
16384 x 2048
Column decoder
Sense amplifier & I(O) bus
16384 x 2048
Column decoder
Sense amplifier & I(O) bus
16384 x 2048
Input buffer
Output buffer
Control logic & timing generator
DQ
0
-DQ
7
RAS
CAS
WE
CK
CK
DLL
Strobe
Gen.
CS
CK, CK
CKE
DM
DQS
Data Strobe
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AS4C128M8D1-6TIN
Signal Pin Description
Pin
CK
CK
CKE
CS
Type
Input
Input
Input
Signal
Pulse
Level
Pulse
Polarity
Positive
Edge
Function
The system clock input. All inputs except DQs and DMs are sampled on the rising edge
of CK.
Active High Activates the CK signal when high and deactivates the CK signal when low, thereby ini-
tiates either the Power Down mode, or the Self Refresh mode.
Active Low CS enables the command decoder when low and disables the command decoder when
high. When the command decoder is disabled, new commands are ignored but previous
operations continue.
Active Low When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the
command to be executed by the SDRAM.
Active High Active on both edges for data input and output.
Center aligned to input data
Edge aligned to output data
—
During a Bank Activate command cycle, A
0
-A
13
defines the row address (RA
0
-RA
13
)
when sampled at the rising clock edge.
During a Read or Write command cycle, A
0
-A
n
defines the column address (CA
0
-CA
n
)
when sampled at the rising clock edge.CAn depends on the SDRAM organization:
128M x 8 DDR CA
n
= CA
9
, A
11
In addition to the column address, A
10
(=AP) is used to invoke autoprecharge operation
at the end of the burst read or write cycle. If A
10
is high, autoprecharge is selected and
BA
0
, BA
1
defines the bank to be precharged. If A
10
is low, autoprecharge is disabled.
During a Precharge command cycle, A
10
(=AP) is used in conjunction with BA
0
and BA
1
to control which bank(s) to precharge. If A
10
is high, all four banks will be precharged
simultaneously regardless of state of BA
0
and BA
1
.
RAS, CAS
WE
DQS
Input
Input/
Output
Input
Pulse
Pulse
A
0
- A
13
Level
BA
0
,
BA
1
DQx
DM,
LDM,
UDM
V
DD
, V
SS
V
DDQ
V
SSQ
V
REF
Input
Input/
Output
Input
Level
Level
Pulse
—
—
Selects which bank is to be active.
Data Input/Output pins operate in the same manner as on conventional DRAMs.
Active High In Write mode, DM has a latency of zero and operates as a word mask by allowing input
data to be written if it is low but blocks the write operation if is high for x 16 LDM
corresponds to data on DQ
0
-DQ
7
, UDM corresponds to data on DQ
8
-DQ
15
.
Power and ground for the input buffers and the core logic.
Supply
Supply
Input
—
Level
—
—
Isolated power supply and ground for the output buffers to provide improved noise
immunity.
SSTL Reference Voltage for Inputs
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