Si5325
µ P - P
ROGRAMMABLE
P
RECISION
C
L O C K
M
ULTIPLIER
Features
Not recommended for new
designs. For alternatives, see the
Si533x family of products.
Generates frequencies from
2 kHz to 945 MHz and select
frequencies to 1.4 GHz from an
input frequency of 10 to 710 MHz
Low jitter clock outputs with jitter
generation as low as 0.5 ps rms
(12 kHz–20 MHz)
Integrated loop filter with
selectable loop bandwidth
(150 kHz to 2 MHz)
Dual clock inputs w/manual or
automatically controlled
switching
Dual clock outputs with
selectable signal format
(LVPECL, LVDS, CML, CMOS)
Support for ITU G.709 and
custom FEC ratios (255/238,
255/237, 255/236)
LOS, FOS alarm outputs
I
2
C or SPI programmable
On-chip voltage regulator for
1.8 ±5%, 2.5 or 3.3 V ±10%
operation
Small size: 6 x 6 mm 36-lead
QFN
Pb-free, ROHS compliant
Ordering Information:
See page 56.
Pin Assignments
CLKOUT1–
CKOUT2+
CMODE
CKOUT2–
SONET/SDH OC-48/STM-16 and
OC-192/STM-64
line cards
GbE/10GbE, 1/2/4/8/10GFC line
cards
ITU G.709 and custom FEC line
cards
NC
36 35 34 33 32 31 30 29 28
RST
NC
INT_C1B
C2B
VDD
GND
NC
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
VDD
VDD
VDD
CLKIN2+
CLKIN1+
CLKIN2–
CLKIN1–
NC
27 SDI
26 A2_SS
25 A1
NC
Optical modules
Wireless basestations
Data converter clocking
xDSL
SONET/SDH + PDH clock synthesis
Test and measurement
GND
CLKOUT1+
24 A0
23 SDA_SDO
22 SCL
21 CS_CA
20 GND
19 GND
Applications
GND
Pad
Description
The Si5325 is a low jitter, precision clock multiplier for applications requiring clock
multiplication without jitter attenuation. The Si5325 accepts dual clock inputs
ranging from 10 to 710 MHz and generates two clock outputs ranging from 2 kHz
to 945 MHz and select frequencies to 1.4 GHz. The two outputs are divided down
separately from a common source. The device provides frequency translation
combinations across this operating range. The Si5325 input clock frequency and
clock multiplication ratio are programmable through an I
2
C or SPI interface. The
Si5325 is based on Silicon Laboratories' 3rd-generation DSPLL
®
technology,
which provides frequency synthesis in a highly integrated PLL solution that
eliminates the need for external VCXO and loop filter components. The DSPLL
loop bandwidth is digitally programmable. Operating from a single 1.8, 2.5, or
3.3 V supply, the Si5325 is ideal for providing clock multiplication in high
performance timing applications
.
GND
NC
Rev. 1.0 9/14
Copyright © 2014 by Silicon Laboratories
NC
VDD
Si5325
Si5325
T
ABLE O F
C
ONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.1. Further Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4. Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
5. Pin Descriptions: Si5325 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
7. Package Outline: 36-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
8. Land Pattern: 36-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
9. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
9.1. Si5325 Top Marking (QFN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
9.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Rev. 1.0
3
Si5325
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Ambient Temperature
Supply Voltage during
Normal Operation
Symbol
T
A
V
DD
3.3 V Nominal
2.5 V Nominal
1.8 V Nominal
Test Condition
Min
–40
2.97
2.25
1.71
Typ
25
3.3
2.5
1.8
Max
85
3.63
2.75
1.89
Unit
C
V
V
V
Note:
All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25 ºC unless otherwise stated.
SIGNAL +
Differential I/Os V , V
OCM
ICM
SIGNAL –
V
V
ISE
, V
OSE
Single-Ended
Peak-to-Peak Voltage
(SIGNAL +) – (SIGNAL –)
V
ICM
, V
OCM
V
ID
,V
OD
t
Differential Peak-to-Peak Voltage
SIGNAL +
SIGNAL –
V
ID
= (SIGNAL+) – (SIGNAL–)
Figure 1. Differential Voltage Characteristics
80%
CKIN, CKOUT
20%
t
F
t
R
Figure 2. Rise/Fall Time Characteristics
4
Rev. 1.0
Si5325
Table 2. DC Characteristics
(V
DD
= 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, T
A
= –40 to 85 °C)
Parameter
Supply Current
1
Symbol
I
DD
Test Condition
LVPECL Format
622.08 MHz Out
Both CKOUTs Enabled
LVPECL Format
622.08 MHz Out
1 CKOUT Enabled
CMOS Format
19.44 MHz Out
Both CKOUTs Enabled
CMOS Format
19.44 MHz Out
1 CKOUT Enabled
Disable Mode
Min
—
Typ
251
Max
279
Unit
mA
—
217
243
mA
—
204
234
mA
—
194
220
mA
—
165
—
mA
CKINn Input Pins
2
Input Common Mode
Voltage (Input Thresh-
old Voltage)
V
ICM
1.8 V ± 5%
2.5 V ± 10%
3.3 V ± 10%
Input Resistance
Single-Ended Input
Voltage Swing
(See Absolute Specs)
CKN
RIN
V
ISE
Single-ended
f
CKIN
< 212.5 MHz
See Figure 1.
f
CKIN
> 212.5 MHz
See Figure 1.
V
ID
f
CKIN
< 212.5 MHz
See Figure 1.
fCKIN > 212.5 MHz
See Figure 1.
0.9
1
1.1
20
0.2
0.25
0.2
0.25
—
—
—
40
—
—
—
—
1.4
1.7
1.95
60
—
—
—
—
V
V
V
k
V
PP
V
PP
V
PP
V
PP
Differential Input
Voltage Swing
(See Absolute Specs)
Notes:
1.
Current draw is independent of supply voltage
2.
No under- or overshoot is allowed.
3.
LVPECL outputs require nominal VDD
≥
2.5 V.
4.
This is the amount of leakage that the 3-Level inputs can tolerate from an external driver. See Si53xx Family Reference
Manual for more details.
5.
LVPECL, CML, LVDS and low-swing LVDS measured with Fo = 622.08 MHz.
Rev. 1.0
5
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