Differential-to-3.3V, 2.5V LVPECL
Clock Divider and Fanout Buffer
8V79S674
DATA SHEET
General Description
The 8V79S674 is a clock divider and fanout buffer. The device has
been designed for clock signal division in wireless base station radio
equipment boards. The device is optimized to deliver excellent
additive phase jitter performance. The 8V79S674 uses SiGe
technology for an optimum of high clock frequency and low phase
noise performance, combined with high power supply noise rejection.
The device offers the frequency division by ÷1, ÷2, ÷4 and ÷8. Four
low-skew LVPECL outputs are available and support clock output
frequencies up to 2500MHz (÷1 frequency division). Outputs can be
disabled to save power consumption if not used. The device is
packaged in a lead-free (RoHS 6) 20-lead VFQFN package. The
extended temperature range supports wireless infrastructure,
telecommunication and networking end equipment requirements.
Features
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Clock signal division and distribution
SiGe technology for high-frequency and fast signal rise/fall times
Four low-skew LVPECL clock outputs
Supports frequency division of ÷1, ÷2, ÷4 and ÷8
Maximum frequency: 2500MHz
Maximum output skew: 50ps (maximum)
Maximum LVPECL output rise/fall time: 200ps (maximum)
3.3V or 2.5V core and output supply mode
Supports 1.8V I/O logic levels for all control pins
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Block Diagram
IN
nIN
2x 50
Pin Assignment
nQ1
nQ2
÷N
Q0
nQ0
15
14
13
12
V
CC
Q1
nQ1
16
17
18
19
20
1
2
3
4
5
V
CC
11
10
9
Q1
Q2
Q3
nQ3
nOEB
N1
V
EE
VT
VREFAC
N[1:0]
nOEA
nOEB
Pulldown
Pulldown
Pulldown
Q0
nQ0
nOEA
Reference Voltage
Q2
nQ2
Q3
nQ3
8V79S674
8
7
6
V
EE
V
REFAC
V
T
nIN
20-pin, 4mm x 4mm VFQFN Package
.
8V79S674 REVISION 2 04/10/15
1
©2015 Integrated Device Technology, Inc.
N0
IN
8V79S674 DATA SHEET
Pin Description and Pin Characteristic Tables
Table 1. Pin Descriptions
Number
1
2
3
4
5, 7
6, 20
8
9, 10
11, 16
12, 13
14, 15
17, 18
19
Name
nIN
V
REFAC
V
T
IN
N0, N1
V
EE
nOEB
nQ3, Q3
V
CC
Q2, nQ2
Q1, nQ1
Q0, nQ0
nOEA
Input
Input
Power
Input
Output
Power
Output
Output
Output
Input
Pulldown
Pulldown
Pulldown
Input
Output
Type
Description
Inverting differential clock signal input. Internal termination 50 to V
T
.
Reference voltage for AC-coupled applications of IN, nIN.
Leave open if IN, nIN is used with LVDS signals. Connect 50 to V
EE
if IN,
nIN is used with LVPECL signals.
Non-inverting differential clock signal input. Internal termination 50 to V
T
.
Frequency divider controls. 1.8V LVCMOS/LVTTL interface levels.
Negative power supply voltage (ground).
Output enable control for the Q1, Q2 and Q3 outputs. 1.8V
LVCMOS/LVTTL interface levels.
Differential clock output pair. LVPECL output levels.
Power supply voltage.
Differential clock output pair. LVPECL output levels
Differential clock output pair. LVPECL output levels
Differential clock output pair. LVPECL output levels
Output enable control for the Q0 output. 1.8V LVCMOS/LVTTL interface
levels.
Exposed package pad negative supply voltage (ground). Return current
path for the Q0, Q1, Q2 and Q3 outputs. This pin must be connected to
ground.
—
V
EE_EP
Power
NOTE:
Pulldown
refers to an internal input resistor. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLDOWN
Parameter
Input Capacitance
Input Pulldown Resistor
Test Conditions
Minimum
Typical
2
51
Maximum
Units
pF
k
DIFFERENTIAL-TO-3.3V, 2.5V LVPECL
CLOCK DIVIDER AND FANOUT BUFFER
2
REVISION 2 04/10/15
8V79S674 DATA SHEET
Truth Tables
Table 3A. Nx Clock Divider Function Table
Input
N1
0 (default)
0
1
1
N0
0 (default)
1
0
1
Divider Value
÷1
÷2
÷4
÷8
Table 3B. nOEA Output Enable Function Table
Input
nOEA
0 (default)
1
Output Operation
Q0 is enabled
Q0 is disabled in logic Low state
Table 3C. nOEB Output Enable Function Table
Input
nOEB
0 (default)
1
Output Operation
Q1, Q2 and Q3 are enabled
Q1, Q2 and Q3 are disabled in logic Low state
REVISION 2 04/10/15
3
DIFFERENTIAL-TO-3.3V, 2.5V LVPECL
CLOCK DIVIDER AND FANOUT BUFFER
8V79S674 DATA SHEET
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of the product at these conditions or any conditions beyond those listed in the
DC Characteristics or
AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Item
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Input Current, IN, nIN
V
T
Current, I
VT
Input Sink/Source, I
REF_AC
T
J
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
CC
+ 0.5V
50mA
100mA
±50mA
±100mA
±2mA
125C
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
CC
= 3.3V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
CC
I
EE
Parameter
Power Supply Voltage
Power Supply Current
Outputs Unloaded
Test Conditions
Minimum
3.135
Typical
3.3
80
Maximum
3.465
90
Units
V
mA
Table 4B. Power Supply DC Characteristics,
V
CC
= 2.5V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
CC
I
EE
Parameter
Power Supply Voltage
Power Supply Current
Outputs Unloaded
Test Conditions
Minimum
2.375
Typical
2.5
75
Maximum
2.625
85
Units
V
mA
Table 4C. LVCMOS/LVTTL DC Characteristics,
V
CC
= 3.3V ± 5% or 2.5V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input High
Current
Input Low
Current
N[1:0],
nOEA, nOEB
N[1:0],
nOEA, nOEB
Test Conditions
V
CC
= 3.3V
V
CC
= 2.5V
1.8V logic
V
CC
= V
IN
= 3.465V or 2.625V
V
CC
= 3.465V or 2.625V, V
IN
= 0V
-10
Minimum
1.2
1.2
-0.3
Typical
Maximum
V
CC
V
CC
0.3
150
Units
V
V
V
µA
uA
DIFFERENTIAL-TO-3.3V, 2.5V LVPECL
CLOCK DIVIDER AND FANOUT BUFFER
4
REVISION 2 04/10/15
8V79S674 DATA SHEET
Table 4D. Differential DC Characteristics,
V
CC
= 3.3V ± 5% or 2.5V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
R
IN
I
IN
V
REFAC
Parameter
Input
Resistance
Input Current
Bias Voltage
IN, nIN
IN, nIN
V
CC
= 2.5V or 3.3V
I
REFAC
= ± 1mA
V
CC
– 1.5
V
CC
– 1.28
Test Conditions
IN to VT, nIN to VT
Minimum
40
Typical
50
Maximum
60
30
V
CC
– 1.0
Units
mA
V
Table 4E. LVPECL DC Characteristics,
V
CC
= 3.3V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
OH
V
OL
V
OUT
V
DIFF_OUT
Parameter
Output High Voltage
1
Output Low Voltage; NOTE 1
Output Voltage Swing
Differential Output Voltage
Swing
Test Conditions
Minimum
V
CC
– 1.1
V
CC
– 1.8
0.5
1
Typical
Maximum
V
CC
– 0.7
V
CC
– 1.4
1
2
Units
V
V
V
V
NOTE 1. Outputs terminated with 50 to V
CC
– 2V.
Table 4F. LVPECL DC Characteristics,
V
CC
= 2.5V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
OH
V
OL
V
OUT
V
DIFF_OUT
Parameter
Output High Voltage
1
Output Low Voltage
1
Output Voltage Swing
Differential Output Voltage
Swing
Test Conditions
Minimum
V
CC
– 1.1
V
CC
– 1.8
0.5
1
Typical
Maximum
V
CC
– 0.7
V
CC
– 1.4
1.0
2
Units
V
V
V
V
NOTE 1. Outputs terminated with 50 to V
CC
– 2V.
REVISION 2 04/10/15
5
DIFFERENTIAL-TO-3.3V, 2.5V LVPECL
CLOCK DIVIDER AND FANOUT BUFFER
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