S29GL01GT/S29GL512T
1 Gbit (128 Mbyte), 512 Mbit (64 Mbyte)
GL-T MirrorBit
®
Eclipse™ Flash
General Description
The Cypress
®
S29GL01GT/512T are MirrorBit
®
Eclipse™ flash products fabricated on 45 nm process technology. These devices
offer a fast page access time as fast as 15 ns, with a corresponding random access time as fast as 100 ns. They feature a Write
Buffer that allows a maximum of 256 words/512 bytes to be programmed in one operation, resulting in faster effective programming
time than standard programming algorithms. This makes these devices ideal for today’s embedded applications that require higher
density, better performance, and lower power consumption.
Distinctive Characteristics
45 nm MirrorBit Eclipse Technology
Single supply (V
CC
) for read / program / erase (2.7 V to
3.6 V)
Versatile I/O feature
– Wide I/O voltage range (V
IO
): 1.65 V to V
CC
x8/x16 data bus
Asynchronous 32-byte Page read
512-byte Programming Buffer
– Programming in Page multiples, up to a maximum of 512
bytes
Single word and multiple program on same word options
Automatic Error Checking and Correction (ECC) — internal
hardware ECC with single bit error correction
Sector Erase
– Uniform 128-kbyte sectors
Suspend and Resume commands for Program and Erase
operations
Status Register, Data Polling, and Ready/Busy pin methods
to determine device status
Advanced Sector Protection (ASP)
– Volatile and non-volatile protection methods for each
sector
Separate 2048-byte One Time Program (OTP) array
– Four lockable regions (SSR0 - SSR3)
– SSR0 is Factory Locked
– SSR3 is Password Read Protect
Common Flash Interface (CFI) parameter table
Temperature Range / Grade:
– Industrial (40 °C to +85 °C)
– Industrial Plus (40 °C to +105 °C)
– Extended (40 °C to +125 °C)
– Automotive, AEC-Q100 Grade 3 (–40 °C to +85 °C)
– Automotive, AEC-Q100 Grade 2 (–40 °C to +105 °C)
100,000 Program / Erase Cycles
20-year data retention
Packaging Options
– 56-pin TSOP
– 64-ball LAA Fortified BGA, 13 mm
11 mm
– 64-ball LAE Fortified BGA, 9 mm
9 mm
– 56-ball VBU Fortified BGA, 9 mm
7 mm
Cypress Semiconductor Corporation
Document Number: 002-00247 Rev. *I
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised May 24, 2017
S29GL01GT/S29GL512T
Performance Summary
Performance Summary for Operating Temperature Range of
40
°C to +85 °C
Maximum Read Access Times
Density
512 Mb
1 Gb
Voltage Range
Full V
CC
= V
IO
Versatile I/O V
IO
Full V
CC
= V
IO
Versatile I/O V
IO
Random Access
Time (t
ACC
)
100
110
100
110
Page Access Time
(t
PACC
)
15
25
15
25
CE# Access Time
(t
CE
)
100
110
100
110
OE# Access Time
(t
OE
)
25
35
25
35
Performance Summary Operating Temperature Range of40 °C to +105 °C
Maximum Read Access Times
Density
512 Mb
1 Gb
Voltage Range
Full V
CC
= V
IO
Versatile I/O V
IO
Full V
CC
= V
IO
Versatile I/O V
IO
Random Access
Time (t
ACC
)
110
120
110
120
Page Access Time
(t
PACC
)
15
25
15
25
CE# Access Time
(t
CE
)
110
120
110
120
OE# Access Time
(t
OE
)
25
35
25
35
Performance Summary Operating Temperature Range of
40
°C to +125 °C
Maximum Read Access Times
Density
512 Mb
1 Gb
Voltage Range
Full V
CC
= V
IO
Versatile I/O V
IO
Full V
CC
= V
IO
Versatile I/O V
IO
Random Access Time
(t
ACC
)
120
130
120
130
Page Access Time
(t
PACC
)
15
25
15
25
CE# Access Time
(t
CE
)
120
130
120
130
OE# Access Time
(t
OE
)
25
35
25
35
Typical Program and Erase Rates
Operation
Buffer Programming (512 bytes)
Sector Erase (128 kbytes)
40
°C to +85 °C
1.14 MB/s
245 kB/s
40
°C to +105 °C
1.14 MB/s
245 kB/s
40
°C to +125 °C
1.14 MB/s
245 kB/s
Maximum Current Consumption
Operation
Active Read at 5 MHz, 30 pF
Program
Erase
Standby
40
°C to +85 °C
60 mA
100 mA
100 mA
100
μA
40
°C to +105 °C
60 mA
100 mA
100 mA
200
μA
40
°C to +125 °C
60 mA
100 mA
100 mA
215
μA
Document Number: 002-00247 Rev. *I
Page 2 of 105
S29GL01GT/S29GL512T
Contents
1.
2.
2.1
2.2
2.3
2.4
2.5
2.6
2.7
3.
3.1
3.2
3.3
3.4
4.
4.1
4.2
5.
5.1
5.2
5.3
5.4
5.5
5.6
5.7
6.
6.1
6.2
7.
7.1
7.2
Product Overview
....................................................... 4
Address Space Overlays
............................................ 6
Flash Memory Array...................................................... 7
Device ID and CFI (ID-CFI) ASO .................................. 8
Status Register ASO..................................................... 9
Data Polling Status ASO............................................... 9
Secure Silicon Region ASO .......................................... 9
Sector Protection Control............................................ 10
ECC Status ASO......................................................... 11
Data Protection
.........................................................
Device Protection Methods .........................................
Command Protection ..................................................
Secure Silicon Region (OTP)......................................
Sector Protection Methods..........................................
12
12
12
12
13
Software Interface
8.4
8.5
8.6
9.
9.1
9.2
9.3
9.4
9.5
10.
10.1
10.2
10.3
10.4
10.5
10.6
11.
11.1
11.2
11.3
11.4
12.
12.1
12.2
12.3
13.
14.
15.
15.1
15.2
15.3
Versatile I/O Feature.................................................... 61
Ready/Busy# (RY/BY#) ............................................... 61
Hardware Reset ........................................................... 61
Signal Protocols.........................................................
62
Interface States............................................................ 62
Power-Off with Hardware Data Protection ................... 63
Power Conservation Modes......................................... 63
Read ............................................................................ 63
Write ............................................................................ 64
Electrical Specifications............................................
65
Absolute Maximum Ratings ......................................... 65
Thermal Resistance ..................................................... 65
Latchup Characteristics ............................................... 65
Operating Ranges........................................................ 66
DC Characteristics ....................................................... 68
Capacitance Characteristics ........................................ 71
Timing Specifications................................................
72
Key to Switching Waveforms ....................................... 72
AC Test Conditions ...................................................... 72
Power-On Reset (POR) and Warm Reset ................... 73
AC Characteristics ....................................................... 75
Physical Interface
...................................................... 90
56-Pin TSOP................................................................ 90
64-Ball FBGA ............................................................... 92
56-Ball FBGA ............................................................... 95
Special Handling Instructions for FBGA Package..
96
Ordering Information
................................................. 97
Other Resources
...................................................... 101
Cypress Flash Memory Roadmap ............................. 101
Links to Software ....................................................... 101
Links to Application Notes.......................................... 101
Read Operations
....................................................... 18
Asynchronous Read.................................................... 18
Page Mode Read ........................................................ 18
Embedded Operations..............................................
Embedded Algorithm Controller (EAC) .......................
Program and Erase Summary ....................................
Automatic ECC ...........................................................
Command Set .............................................................
Status Monitoring ........................................................
Error Types and Clearing Procedures ........................
Embedded Algorithm Performance Table...................
19
19
19
21
22
36
41
44
Data Integrity
............................................................. 47
Erase Endurance ........................................................ 47
Data Retention ............................................................ 47
Software Interface Reference
.................................. 48
Command Summary ................................................... 48
Device ID and Common Flash Interface (ID-CFI) ASO
Map ............................................................................ 55
Signal Descriptions
..................................................
Address and Data Configuration.................................
Input/Output Summary................................................
Word/Byte Configuration.............................................
60
60
60
61
Hardware Interface
8.
8.1
8.2
8.3
16. Document History Page
.......................................... 102
Sales, Solutions, and Legal Information .........................105
Worldwide Sales and Design Support ......................... 105
Products ...................................................................... 105
PSoC® Solutions ........................................................ 105
Cypress Developer Community ................................... 105
Technical Support ....................................................... 105
Document Number: 002-00247 Rev. *I
Page 3 of 105
S29GL01GT/S29GL512T
1.
Product Overview
The GL-T family consists of 512-Mbit to 1-Gbit, 3.0 V core, Versatile I/O, non-volatile, flash memory devices. These devices have an
8-bit (byte) / 16-bit (word) wide data bus and use only byte / word boundary addresses. All read accesses provide 8/16 bits of data
on each bus transfer cycle. All writes take 8/16 bits of data from each bus transfer cycle.
Figure 1.1
Block Diagram
RY/BY#
V
CC
V
SS
V
IO
RESET#
Erase Voltage
Generator
Input/Output
Buffers
Sector Switches
DQ15 - DQ0
WE#
WP#/ACC
BYTE#
State
Control
Command
Register
PGM Voltage
Generator
Chip Enable
Output Enable
Logic
STB
Data
Latch
CE#
OE#
Y-Decoder
STB
Y-Gating
Address Latch
V
CC
Detector
Timer
X-Decoder
Cell Matrix
** Amax – A0 (A-1)
:
Note:
** Amax GL01GT = A25, Amax GL512T = A24.
The GL-T family combines the best features of eXecute In Place (XIP) and Data Storage flash memories. This family has the fast
random access of XIP flash along with the high density and fast program speed of Data Storage flash.
Read access to any random location takes 100 ns to 120 ns depending on device density and I/O power supply voltage. Each
random (initial) access reads an entire 32-byte aligned group of data called a Page. Other words within the same Page may be read
by changing only the low order 4 bits of word address. Each access within the same Page takes 15 ns to 25 ns. This is called Page
Mode read. Changing any of the higher word address bits will select a different Page and begin a new initial access. All read
accesses are asynchronous.
Document Number: 002-00247 Rev. *I
Page 4 of 105
S29GL01GT/S29GL512T
Table 1.1 S29GL-T Address Map
x16
Type
Address within Page
Address within Write Buffer
Page
Write-Buffer-Line
Sector
Count
16
256
4096 per Sector
256 per Sector
1024 (1 Gb)
512 (512 Mb)
Addresses
A3–A0
A7–A0
A15–A4
A15–A8
Amax–A16
Count
32
512
4096 per Sector
256 per Sector
1024 (1 Gb)
512 (512 Mb)
x8
Addresses
A3–A1
A7–A1
A15–A4
A15–A8
Amax–A16
The device control logic is subdivided into two parallel operating sections, the Host Interface Controller (HIC) and the Embedded
Algorithm Controller (EAC). HIC monitors signal levels on the device inputs and drives outputs as needed to complete read and write
data transfers with the host system. HIC delivers data from the currently entered address space on read transfers; places write
transfer address and data information into the EAC command memory; notifies the EAC of power transition, hardware reset, and
write transfers. The EAC looks in the command memory, after a write transfer, for legal command sequences and performs the
related Embedded Algorithms.
Changing the non-volatile data in the memory array requires a complex sequence of operations that are called Embedded
Algorithms (EA). The algorithms are managed entirely by the device internal EAC. The main algorithms perform programming and
erase of the main array data. The host system writes command codes to the flash device address space. The EAC receives the
commands, performs all the necessary steps to complete the command, and provides status information during the progress of an
EA.
The erased state of each memory bit is a logic 1. Programming changes a logic 1 (High) to a logic 0 (Low). Only an Erase operation
is able to change a 0 to a 1. An erase operation must be performed on an entire 128-kbyte aligned and length group of data call a
Sector. When shipped from Cypress all Sectors are erased.
Programming is done via a 512-byte Write Buffer. In x16 it is possible to write from 1 to 256 words, anywhere within the Write Buffer
before starting a programming operation. Within the flash memory array, each 512-byte aligned group of 512 bytes is called a Line.
In x8 it is possible to write from 1 to 256 bytes, anywhere within the Write Buffer before starting a program operation. A programming
operation transfers volatile data from the Write Buffer to a non-volatile memory array Line. The operation is called Write Buffer
Programming.
As the device transfers each 32-byte aligned page of data that was loaded into the Write buffer to the 512-byte Flash array line,
internal logic programs an ECC Code for the Page into a portion of the memory array not visible to the host system software. The
internal logic checks the ECC information during the initial access of every array read operation. If needed, the ECC information
corrects a one bit error during the initial access time.
The Write Buffer is filled with 1’s after reset or the completion of any operation using the Write Buffer. Any locations not written to a 0
by a Write to Buffer command are by default still filled with 1’s. Any 1’s in the Write Buffer do not affect data in the memory array
during a programming operation.
As each Page of data that was loaded into the Write Buffer is transferred to a memory array Line.
Sectors may be individually protected from program and erase operations by the Advanced Sector Protection (ASP) feature set.
ASP provides several, hardware and software controlled, volatile and non-volatile, methods to select which sectors are protected
from program and erase operations.
Document Number: 002-00247 Rev. *I
Page 5 of 105
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