Sales, Solutions, and Legal Information ........................... 74
2.
3.
4.
5.
Document Number: 002-03238 Rev. *E
Page 2 of 74
S34MS01G2
S34MS02G2
S34MS04G2
1. General Description
The Cypress S34MS01G2, S34MS02G2, and S34MS04G2 series is offered in 1.8 V
CC
and V
CCQ
power supply, and with x8 or x16
I/O interface. Its NAND cell provides the most cost-effective solution for the solid state mass storage market. The memory is divided
into blocks that can be erased independently so it is possible to preserve valid data while old data is erased. The page size for x8 is
(2048 + spare) bytes; for x16 (1024 + spare) words.
Each block can be programmed and erased up to 100,000 cycles with ECC (error correction code) on. To extend the lifetime of
NAND flash devices, the implementation of an ECC is mandatory.
The chip supports CE# don't care function. This function allows the direct download of the code from the NAND flash memory device
by a microcontroller, since the CE# transitions do not stop the read operation.
The devices have a Read Cache feature that improves the read throughput for large files. During cache reading, the devices load
the data in a cache register while the previous data is transferred to the I/O buffers to be read.
Like all other 2-kB page NAND flash devices, a program operation typically writes 2 KB (x8), or 1 kword (x16) in 300 µs and an erase
operation can typically be performed in 3 ms (S34MS01G2) on a 128-kB block (x8) or 64-kword block (x16). In addition, thanks to
multiplane architecture, it is possible to program two pages at a time (one per plane) or to erase two blocks at a time (again, one per
plane). The multiplane architecture allows program time to be reduced by 40% and erase time to be reduced by 50%.
In multiplane operations, data in the page can be read out at 45 ns cycle time per byte. The I/O pins serve as the ports for command
and address input as well as data input/output. This interface allows a reduced pin count and easy migration towards different
densities, without any rearrangement of the footprint.
Commands, Data, and Addresses are asynchronously introduced using CE#, WE#, ALE, and CLE control pins.
The on-chip Program/Erase Controller automates all read, program, and erase functions including pulse repetition, where required,
and internal verification and margining of data. A WP# pin is available to provide hardware protection against program and erase
operations.
The output pin R/B# (open drain buffer) signals the status of the device during each operation. It identifies if the program/erase/read
controller is currently active. The use of an open-drain output allows the Ready/Busy pins from several memories to connect to a
single pull-up resistor. In a system with multiple memories the
R/B# pins can be connected all together to provide a global status signal.
The Reprogram function allows the optimization of defective block management — when a Page Program operation fails the data
can be directly programmed in another page inside the same array section without the time consuming serial data insertion phase.
Multiplane Copy Back is also supported. Data read out after Copy Back Read (both for single and multiplane cases) is allowed.
In addition, Cache Program and Multiplane Cache Program operations improve the programing throughput by programing data
using the cache register.
The devices provide two innovative features: Page Reprogram and Multiplane Page Reprogram. The Page Reprogram re-programs
one page. Normally, this operation is performed after a failed Page Program operation. Similarly, the Multiplane Page Reprogram re-
programs two pages in parallel, one per plane. The first page must be in the first plane while the second page must be in the second
plane. The Multiplane Page Reprogram operation is performed after a failed Multiplane Page Program operation. The Page
Reprogram and Multiplane Page Reprogram guarantee improved performance, since data insertion can be omitted during re-
program operations.
Document Number: 002-03238 Rev. *E
Page 3 of 74
S34MS01G2
S34MS02G2
S34MS04G2
The devices come with the following security features:
OTP (one time programmable) area, which is a restricted access area where sensitive data/code can be stored permanently.
Serial number (unique identifier), which allows the devices to be uniquely identified. Contact factory for support of this feature.
These security features are subject to an NDA (non-disclosure agreement) and are, therefore, not described in the data sheet. For
more details about them, contact your nearest Cypress sales office.
Device
Density (bits)
Main
128M x 8
64M x 16
256M x 8
128M x 16
512M x 8
256M x 16
Spare
4M x 8
2M x 16
16M x 8
8M x 16
32M x 8
16M x 16
Number of Planes
Number of Blocks per Plane
S34MS01G2
S34MS02G2
S34MS04G2
1
2
2
1024
1024
2048
1.1
Logic Diagram
Figure 1.1
Logic Diagram
VCC
VCCQ
CE#
WE#
RE#
ALE
CLE
WP#
I/O0~I/O7
I/O8~I/O15 (x16 only)
R/B#
VSS
VSSQ
Table 1.1
Signal Names
I/O7 - I/O0
(x8)
I/O8 - I/O15
(x16)
CLE
ALE
CE#
RE#
WE#
WP#
R/B#
VCC
VSS
NC
Data Input / Outputs
Command Latch Enable
Address Latch Enable
Chip Enable
Read Enable
Write Enable
Write Protect
Read/Busy
Power Supply
Ground
Not Connected
Document Number: 002-03238 Rev. *E
Page 4 of 74
S34MS01G2
S34MS02G2
S34MS04G2
1.2
Connection Diagram
Figure 1.2
48-Pin TSOP1 Contact x8, x16 Devices
x16
NC
NC
NC
NC
NC
NC
R/B#
RE#
CE#
NC
NC
VCC
VSS
NC
NC
CLE
ALE
WE#
WP#
NC
NC
NC
NC
NC
x8
NC
NC
NC
NC
NC
NC
R/B#
RE#
CE#
NC
NC
VCC
VSS
NC
NC
CLE
ALE
WE#
WP#
NC
NC
NC
NC
NC
x8
x16
VSS
I/O15
I/O14
I/O13
I/O7
I/O6
I/O5
I/O4
I/O12
VCC
NC
VCC
VSS
NC
VCC
I/011
I/O3
I/O2
I/O1
I/O0
I/O10
I/O9
I/O8
VSS
1
48
12
13
NAND Flash
TSOP1
37
36
24
25
VSS
(1)
NC
NC
NC
I/O7
I/O6
I/O5
I/O4
NC
VCC
(1)
NC
VCC
VSS
NC
VCC
(1)
NC
I/O3
I/O2
I/O1
I/O0
NC
NC
NC
VSS
(1)
Note:
1. These pins should be connected to power supply or ground (as designated) following the ONFI specification, however they might not be bonded internally.
[font=微软雅黑][size=3]I blame myself for not having enough education. Today I learned that April 30th is International Day Against Sparing[/size][/font]{:1_104:}[font=微软雅黑][size=3] [/size][/font] [font=微...
1. B&O Beoplay E8 unboxing [align=center][/align] [align=left]The charging port uses Micro USB, and there are two hidden white indicator lights on the right. When charging, one white light flashes, an...
The control system of a production workshop of my company uses Modicon 984-785E series PLC. It has been in operation for nearly 15 years since 1996. Recently, a strange fault occurred. After a certain...
After WinCE is running, the fonts on the screen flicker violently horizontally and jitter vertically. Is it because the 2440 has poor anti-interference ability at the non-industrial level?...
Talking
京公网安备 11010802033920号
EEWORLD
