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dsPIC33FJ16GS502-50I/SO

Description
Digital Signal Processors and Controllers-DSP, DSC 16B MCU/DSP 50MIPS 16KB FL SMPS
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size3MB,399 Pages
ManufacturerMicrochip
Websitehttps://www.microchip.com
Environmental Compliance
Download Datasheet Download user manual Parametric View All

dsPIC33FJ16GS502-50I/SO Overview

Digital Signal Processors and Controllers-DSP, DSC 16B MCU/DSP 50MIPS 16KB FL SMPS

dsPIC33FJ16GS502-50I/SO Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerMicrochip
package instructionSOIC-28
Reach Compliance Codecompliant
Factory Lead Time11 weeks
Has ADCYES
Address bus width
barrel shifterYES
bit size16
boundary scanYES
maximum clock frequency50 MHz
DAC channelNO
DMA channelNO
External data bus width
FormatFIXED POINT
Integrated cacheNO
Internal bus architectureMULTIPLE
JESD-30 codeR-PDSO-G28
JESD-609 codee3
length10.3 mm
low power modeYES
Humidity sensitivity level1
Number of external interrupt devices3
Number of I/O lines21
Number of terminals28
Number of timers3
On-chip data RAM width8
On-chip program ROM width8
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
PWM channelYES
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Encapsulate equivalent codeSOP28,.4
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Peak Reflow Temperature (Celsius)250
RAM (number of words)2048
ROM programmabilityFLASH
Filter levelTS 16949
Maximum seat height2.65 mm
speed40 MHz
Maximum slew rate160 mA
Maximum supply voltage3.6 V
Minimum supply voltage3 V
Nominal supply voltage3.3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceMatte Tin (Sn) - annealed
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperature40
width7.5 mm
uPs/uCs/peripheral integrated circuit typeDIGITAL SIGNAL PROCESSOR, OTHER
Base Number Matches1
dsPIC33FJ06GS101/X02 and
dsPIC33FJ16GSX02/X04
16-Bit Digital Signal Controllers (up to 16-Kbyte Flash and up to
2-Kbyte SRAM) with High-Speed PWM, ADC and Comparators
Operating Conditions
• 3.0V to 3.6V, -40ºC to +150ºC, DC to 20 MIPS
• 3.0V to 3.6V, -40ºC to +125ºC, DC to 40 MIPS
• 3.0V to 3.6V, -40ºC to +85ºC, DC to 50 MIPS
Advanced Analog Features (Continued)
• Up to Four High-Speed Comparators with Direct
Connection to the PWM module:
- Programmable references with 1024 voltage points
Core: 16-Bit dsPIC33F CPU
Code-Efficient (C and Assembly) Architecture
Two 40-Bit Wide Accumulators
Single-Cycle (MAC/MPY) with Dual Data Fetch
Single-Cycle Mixed-Sign MUL plus Hardware Divide
32-Bit Multiply Support
Timers/Output Compare/Input Capture
• Three General Purpose Timers:
- Three 16-bit and one 32-bit timer/counter
• Two Output Compare (OC) modules
• Two Input Capture (IC) modules
• Peripheral Pin Select (PPS) to allow Function Remap
Clock Management
±2.0% Internal Oscillator
Programmable PLLs and Oscillator Clock Sources
Fail-Safe Clock Monitor (FSCM)
Independent Watchdog Timer (WDT)
Fast Wake-up and Start-up
Communication Interfaces
• UART module (12.5 Mbps):
- With support for LIN/J2602 protocols and IrDA
®
• 4-Wire SPI module
• I
2
C™ module (up to 1 Mbaud) with SMBus Support
• PPS to allow Function Remap
Power Management
• Low-Power Management modes (Sleep, Idle, Doze)
• Integrated Power-on Reset and Brown-out Reset
Input/Output
• Sink/Source 18 mA on 8 Pins, 10 mA on 10 Pins
and 6 mA on 17 Pins
• 5V Tolerant Pins
• Selectable Open-Drain and Pull-ups
• External Interrupts on up to 30 I/O Pins
High-Speed PWM
Up to Four PWM Pairs with Independent Timing
Dead Time for Rising and Falling Edges
1.04 ns PWM Resolution
PWM Support for:
- DC/DC, AC/DC, Inverters, PFC and Lighting
• Programmable Fault Inputs
• Flexible Trigger Configurations for ADC Conversions
Qualification and Class B Support
AEC-Q100 REVG (Grade 1, -40ºC to +125ºC)
AEC-Q100 REVG (Grade 0, -40ºC to +150ºC)
Class B Safety Library, IEC 60730, VDE Certified
6x6x0.5 mm UQFN Package Designed and
Optimized to ease IPC9592A 2nd Level Temperature
Cycle Qualification
Advanced Analog Features
• ADC module:
- 10-bit resolution with up to 2 Successive Approximation
Register (SAR) converters (4 Msps) and up to
six Sample-and-Hold (S&H) circuits
- Up to 12 input channels grouped into six conversion
pairs, plus two voltage reference monitoring inputs
- Dedicated result buffer for each analog channel
• Flexible and Independent ADC Trigger Sources
Debugger Development Support
In-Circuit and In-Application Programming
Two Breakpoints
IEEE 1149.2-Compatible (JTAG) Boundary Scan
Trace and Run-Time Watch
2008-2014 Microchip Technology Inc.
DS70000318G-page 1
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