EVBUM2257/D
Full Frame Image Sensors
Evaluation Board
User's Manual
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Introduction
The Full Frame Evaluation Board provides a powerful
platform to quickly and easily evaluate a number of
ON Semiconductor Full Frame Image Sensors in
a prototype imaging system. The Evaluation Kit also serves
as a useful reference design that will save considerable time
and cost in the development of a product prototype.
The programmable logic architecture, bias supplies, clock
drivers and analog signal processing chain can be readily
used, with application specific modifications, in a camera
production design.
The Evaluation Board is designed to be flexible, and has
the ability to operate many different Full Frame image
sensors at different operating frequencies. Consult
ON Semiconductor to obtain information for optimizing the
reference design to operate a specific image sensor at
a specific operating frequency.
EVAL BOARD USER’S MANUAL
Overview
The Full Frame Evaluation Board serves as a complete,
self-contained, CCD image acquisition sub-system.
The user simply applies power, and an IMAGE_AQUIRE
TTL pulse to begin capturing digital images. Differential
TTL frame grabber sync pulses (Frame, Pixel and Line rate)
are provided to facilitate easy connection to a frame grabber.
In the still capture mode, application of the
IMAGE_ACQUIRE signal results in flushing of the CCD,
then integration, then clocking out of a full frame of image
data. In free-run mode, an acquisition signal is not needed;
the board is free running and continuous frames of 12 bit
information stream out.
12 Bit Output
Image_Acquire
CCD Reference
Evaluation Board
Figure 1. Block Diagram (Overview)
SPECIFICATIONS
Maximum Data Rate:
6 MHz
Resolution:
12 Bits
Frame Rate:
Depends on Data Rate, CCD Array Size,
and Integration Time
Outputs
Inputs
D[11..0]:
Frame Grabber Syncs:
Integration Sync:
Differential TTL
Differential TTL
TTL
Serial Clock:
PGA Gain Range:
PGA Gain Resolution:
Offset Range:
Offset Resolution:
Temperature Range Board:
Temperature Range CCD:
10 MHz Maximum
1X to 6X
256 Steps
−100 mV to +100 mV
256 Steps
0 – 70°C
−50 to +70°C Typical
©
Semiconductor Components Industries, LLC, 2014
1
September, 2014 − Rev. 2
Publication Order Number:
EVBUM2257/D
EVBUM2257/D
Table 1. POWER SUPPLY REQUIREMENTS
Power Supplies
Supply
+5 V
+18 V
−18 V
Minimum
+4.9 V
+17 V
−20 V
Nominal
+5 V
+18 V
−18 V
Maximum
+5.1 V
+20 V
−13 V
Typical Current
Switching Power Supply
Disabled
1000 mA
120 mA
100 mA
Enabled
1500 mA
−
−
Electrons per A/D count − 29.2 @ 5 MHz, 2.5X Gain setting
(Assuming on-chip CCD amplifier gain CCD of
10
mV/electron).
RMS Dark Noise − 1.9 LSB typical @ 5 MHz, 2.5X Gain
setting.
System Noise Floor − 56 electrons @ 5 MHz, 2.5X Gain
setting (Assuming on-chip CCD amplifier gain of
10
mV/electron).
ARCHITECTURE OVERVIEW
A complete Block Diagram of the Evaluation Board is
shown in Figure 3.
Master Clock
a three wire serial interface. Additionally, if the user chooses
to adjust the AD9816’s register settings, the PLD2 controls
the programming of these registers.
CCD Clock Drivers
The Master Clock runs at eight times the Pixel clock
frequency. The maximum pixel clock frequency is 6 MHz,
which yields a maximum system clock frequency of
48 MHz. For slower Pixel clock frequencies, decrease the
master clock frequency. The Default setting of the
evaluation board is a 40 MHz system clock, with a pixel
clock frequency of 5 MHz.
The KAF−4301 is an exception to this. It provides pixel
frequencies of 2.5 MHz and 1.25 MHz by dividing the
40 MHz master clock by 16 and 32. The pixel frequency is
selected using SW2. This is an 8-position switch that usually
selects a CCD binning mode (See section Binning Modes).
The KAF−4301 timing program does not support binning at
this time and, instead, uses this switch to select the pixel rate
(See Table 8). The pixel rate is 1.25 MHz when SW2 is set
to position 0 and 2.5 MHz when set in any other position.
PLD1
PLD1 contains the Clocking State Machine that controls
the operational flow of the evaluation board (Figure 4).
PLD1 generates the CCD clock timing, A/D converter
timing and frame grabber sync signals. The PLD1 controls
the image line and frame length [dependent upon the CCD
switch settings], as well as the horizontal and vertical CCD
clock timing [dependent upon the binning mode BIN switch
settings.]
PLD2
Elantec clock drivers, designed to drive the large
capacitance loads presented by the clock gates of the CCD,
are used to generate the horizontal and vertical clocks.
The Elantec drivers accept TTL inputs, and level shift to the
required peak-to-peak voltage swing of the CCD clocks.
The peak-to-peak swing of the clocks is adjustable.
The outputs of the drivers are AC coupled, providing
adjustable offset of the clocks from the negative rail to the
positive rail. Using a separate IC for each vertical clock (V1,
V2), a maximum 4 amp output drive current per vertical
clock channel is available. A single IC is used to drive H1,
and H2, giving a maximum 2 A output drive current per
Horizontal clock channel.
The reset clock driver utilizes two fast switching
transistors, designed for a fast switching input signal with
a narrow pulse width. The peak-to-peak voltage swing and
the offset voltage are adjustable.
CCD Bias Voltages
CCD bias voltages (VRD, VOG, VLG) are supplied by
filtered outputs of adjustable potentiometers. Fixed CCD
bias voltages (LOD, VSS, GUARD) are supplied by filtered
outputs of voltage dividers.
CCD Image Sensor
PLD2 controls the integration timing, which is dependent
upon the INT switch settings. PLD2 also programs the
AD9816’s registers to a default condition upon power up via
This evaluation board supports the following Full Frame
CCD image sensors: KAF−0261, KAF−0402, KAF−1001,
KAF−1603, KAF−3200, KAF−6303, KAF−16801,
and KAF−4301.
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EVBUM2257/D
A/D Converter Analog Devices AD9816
The AD9816 is a 12 bit, 6 MSPS CCD analog signal
processor. The IC provides an integrated correlated double
sampling (CDS), 8 bit programmable gain, and 8 bit DC
offset adjust. Timing signals are provided by PLD1. Default
register values are downloaded from PLD2 upon power up.
Alternate programming of its registers can be achieved via
external serial interface or by manually setting the address
and data switches on the board and pressing the capture
button.
Emitter Follower
The circuit is set to toggle at 100 Hz, providing a fixed unit
integration time of 10 ms. The actual integration time is set
to a multiple of the unit integration time using an internal
integration counter in PLD2. The user can choose an
integration time from 10 ms to 10 seconds by setting the
integration switches appropriately (See Table 9).
J6 Input Connector
The video out of the CCD is buffered using a bipolar
junction transistor in the emitter follower configuration.
AC Coupling Capacitor
This connector is used to input control signals to the
evaluation board. This is an optional feature; all control lines
can be set via on-board switches. Images can be acquired
using the on-board image capture button. No external digital
inputs are needed to acquire images.
J4 Output Connector
A 1200 pF input coupling capacitor removes the DC
component of the video signal.
Power On Clear/Reset
The J4 output connector provides 12 bits of video data in
RS422 differential TTL format. J4, additionally, provides
three frame grabber sync signals in differential TTL format.
J7 Integration Sync
Resets and initializes the board on power up or when the
Reset button in pressed.
JTAG Header
A 10-pin header provides the user with the ability to
reprogram the Altera 7000S PLDs in system via Altera’s
ByteBlaster programming hardware.
Unit Integration Time
This connector provides a sync signal that is high during
the integration time period. The signal can be used to sync
a shutter or LED light source to the evaluation board, and can
source up to 80 mA at 5 V.
J1, J2 Imager Board Connectors
The amount of time the CCD is exposed to light before
clocking out the accumulated charge is called the integration
time. An RC circuit and Schmitt trigger inverter are used to
set the unit integration time. Total integration time is
a multiple of the unit integration time.
CCD Daughter Boards plug into these connectors.
The daughter boards route the clock and bias traces from the
timing board to the proper pins of the CCD.
Power Supplies
Altera Timing
Integrate
An onboard switching supply provides all of the voltages
necessary to operate the CCD Digital Reference Evaluation
Board, from a single +5 V source.
Switching supplies can, however, be a source of low-level
asynchronous noise. If asynchronous noise is present and
objectionable in an application, the internal switching
supply can be disabled and external low-noise linear
supplies can be used to power the board. The procedure for
configuring the board to accept external supplies is detailed
Under Power Supply Modes
J5 Power Connector
R
POT
C1
The power connector is a 5-pin connector with +5 V,
+18 V, −18 V and two AGND connections. If the switching
power supply is used to generate the +15 V and −10 V
supplies, then only an external +5 V supply needs to be
brought in through J5. Otherwise, all three power supplies
must be connected to the board via J5.
Set Unit Integration
Figure 2. Unit Integration Timing Adjustment
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EVBUM2257/D
BOARD REQUIREMENTS
Power Supply
The board requires only a single +5 V, 1.5 Amp or greater
power supply to operate. An on board switching power
supply generates the necessary +15 V, 120 mA and –10 V,
120 mA power supplies from the 5 V input. Although
extensive filtering is done on board, the power supplied to
the board must be quiet and stable in order to achieve the best
possible performance. (See Power Supply Modes, for an
alternative way to power the board.)
Inputs
INTEGRATE − A signal provided to allow the user to
synchronize the strobing of LED illuminators or opening of
a shutter, during the integration period.
FRAME (±)* − Differential TTL Frame grabber vertical
sync signal.
LINE (±)* − Differential TTL Frame grabber horizontal
sync signal.
PIX (±)* − Differential TTL Frame grabber pixel sync
*These sync signals can be modified if necessary to accommodate
different Frame Grabbers.
In the Free-Run mode, the evaluation board requires no
input signals to begin acquiring images.
In Still mode, the evaluation board will acquire a single
image on the falling edge of the Image_Acquire control line.
This can be accomplished via the push button (S4) or,
remotely, by utilizing the Image_Acquire control line.
See Section Still/Free-Run Modes for more information
on Still and Free-Run modes.
See Sections Line/Switches Modes and AD_IN/EX
Modes for information on additional optional inputs.
Outputs
JTAG Programming
Altera 7000S In System Programmable (ISP) PLD’s are
used on this board. A ten-pin header (J8) is provided to allow
for the programming of these PLD’s. Since these parts are
re-programmable, custom digital logic can be implemented
for timing and mode adjustments or additions. Any custom
implementation can be made quickly and easily to via the
JTAG programming interface provided by this connector.
D[11..0] (±) − 12 bits of Differential TTL Digital
information
CONFIGURATION MODES
The following modes of operation are available to the
user:
Line/Switches Modes
The Line/Switches Jumper (SW5) selects whether some
of the board settings will be controlled externally through
the J6 connector (Line), or via the on-board switches
(Switches). If this switch is set to Line, then the integration
time and the binning mode must be set remotely via digital
I/O. The still/free-run mode switch (SW3, 3-position
switch) can also be set externally when the Line mode is
selected. Set SW3 to the middle position if it is desired to
control this line externally.
Still/Free-Run Modes
accomplished by either pressing the on-board acquire button
(S4) or, remotely, bringing the Image_Acquire line low and
then back high. The detection of the falling edge of this
signal starts the image acquisition process.
The still mode acquisition process is as follows:
1. The CCD is flushed of all accumulated charge.
2. The CCD is exposed to light during the integration
time.
3. The image is clocked out of the CCD. The system
then waits for the next Image_Acquire signal.
In the Free-Run mode, the system will continuously
capture images and clock them out. No flushing is done, as
the clocking out of the previous image serves this same
purpose.
See Figure 4 for the Clocking State Machine Diagram.
AD_IN/EX Modes
The “Still/Free-Run” switch (SW3) is a three-position
switch that selects whether the board will operate in the still
mode, or a free-running mode.
If SW3 is placed in the middle position (“LINE”),
the image capture mode is determined by the voltage on the
STILL/FREE-RUN pin on the input connector (J6−27).
Setting this line LOW selects the free-run mode, and setting
it HIGH selects the still mode.
In still mode, the Image_Acquire control line must be
strobed in order to acquire a single image. This is
The board comes with an Analog Devices AD9816 12 bit
A/D converter on board. This A/D has several features, such
as multiple configurations, programmable gain, and offset
registers which require initialization and/or programming
on power up. The programming of these registers is done via
a three wire serial interface.
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EVBUM2257/D
EXT
A three wire serial interface is provided on the J6
connector of the board, and the AD9816 registers can be
controlled remotely via these when the A/D_IN/EX Jumper
(SW4) is set to EXT. See Figure 5 for AD9816 serial timing
diagrams and information.
INT
Frame Grabber Diagnostic Modes
If it is not desired to control the programming of the A/D’s
registers remotely, set Jumper SW4 to INT. PLD2 contains
a state machine that serially loads in the following default
values to these registers upon power up.
A/D Default Register Settings:
No. of channels:
1
Mode:
CDS Mode
Input Span:
3V
Channel Selected: Green
Red PGA Gain*:
1
Green PGA Gain: 1
Blue PGA Gain*: 1
Red Offset*:
0 mv
Green Offset:
0 mv
Blue Offset*:
0 mv
*Although the Red and Blue channels are not used, these registers
are still initialized to these default settings.
When set to ENABLE, the Sync_Test_Enable switch
(SW12) tri-states the 12-bit output bus out of the A/D
converter, and enables the output of either the pixel number
or the line number onto the output bus, depending on how the
Sync_Test_pix/line Jumper is set (SW11). This provides
a diagnostic test to make certain the Frame Grabber is
synchronized correctly with the board.
The line counter in PLD1 is a binary up-counter, therefore
the line count that is output to the output bus will increment
sequentially (0, 1, 2, 3, 4, 5...) until the last line in the frame.
The pixel counter in PLD1 is a gray code up counter,
therefore the pixel count that is output to the output bus will
increment in gray code transition counts (0, 1, 3, 2, 6, 7, 5,
4...) until the last pixel in the line.
Power Supply Modes
Power can be supplied to the board in one of two ways:
Switching Power Supply
Adjustments
Adjustments can be made to the A/D registers during
operation of the board by utilizing the DATA dipswitch
(SW10), the ADDRESS switch (SW9), and the
Image_Acquire control line. After setting SW9 to the
desired Address, and SW10 to the desired Data, send an
Image_Acquire signal either by pressing the
Image_Acquire button or remotely via the J6 connector
control line. This will load the new value into PLD2 and
a state machine inside the PLD will then serial load the new
data into the A/D’s register. This is true whether or not the
board is running in Still or Free Run Mode. (See Figure 5 for
more information on the AD9816 registers.)
CCD Modes
The board comes supplied with a 500 kHz switching
power supply (Linear Technologies LT1372). If it is desired
to utilize the on-board switching supply, the board should be
configured as follows:
1. Connect a 5 V, 1.5 A or greater lab supply to the J5
power connector.
2. Install Jumper 6 and Jumper 4.
3. Remove Jumper 7 and Jumper 5.
4. Set Jumper 1 to the ON position.
External Supply Operation
To disable the on-board switching supply and operate
using external supplies:
1. Remove Jumpers 4 and 6;
2. Install Jumpers 5 and 7;
3. Move Jumper 1 to the “OFF” position to disable
the switching power supply;
4. Connect +18 V, −18 V, and +5 V to power input
connector J5.
Functionality
The CCD Select switch (SW1) setting determines the line
and frame length timing.
This switch is pre-set at ON Semiconductor. (See Table 5)
Binning Modes
The BIN Select switch (SW2) setting determines the
Binning mode operation. (Table 6)
Integration Modes
The switching supply generates +15 V and –10 V supply
“islands”. The same is true for the +15 V and –10 V
regulators on the board. Jumpers 4 and 6 connect the
switcher supplies to the +15 V, −10 V power plane.
Jumpers 5 and 7 connect the regulated outputs to the +15 V,
−10 V power plane. Jumper 1 either enables or disables the
LT1372 Switcher.
The INT Select switches (SW6, SW7) settings determine
the Integration Time.
SW6 is the Coarse Adjust. SW7 is the Fine Adjust.
(Table 9)
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