PCA9533
4-bit I
2
C-bus LED dimmer
Rev. 03 — 27 April 2009
Product data sheet
1. General description
The PCA9533 is a 4-bit I
2
C-bus and SMBus I/O expander optimized for dimming LEDs in
256 discrete steps for Red/Green/Blue (RGB) color mixing and back light applications.
The PCA9533 contains an internal oscillator with two user programmable blink rates and
duty cycles coupled to the output PWM. The LED brightness is controlled by setting the
blink rate high enough (> 100 Hz) that the blinking cannot be seen and then using the duty
cycle to vary the amount of time the LED is on and thus the average current through the
LED.
The initial setup sequence programs the two blink rates/duty cycles for each individual
PWM. From then on, only one command from the bus master is required to turn individual
LEDs ON, OFF, BLINK RATE 1 or BLINK RATE 2. Based on the programmed frequency
and duty cycle, BLINK RATE 1 and BLINK RATE 2 will cause the LEDs to appear at a
different brightness or blink at periods up to 1.69 second. The open-drain outputs directly
drive the LEDs with maximum output sink current of 25 mA per bit and 100 mA per
package.
To blink LEDs at periods greater than 1.69 second the bus master (MCU, MPU, DSP,
chip set, etc.) must send repeated commands to turn the LED on and off as is currently
done when using normal I/O expanders like the NXP Semiconductors PCF8574 or
PCA9554. Any bits not used for controlling the LEDs can be used for General Purpose
parallel Input/Output (GPIO) expansion, which provides a simple solution when additional
I/O is needed for ACPI power switches, sensors, push-buttons, alarm monitoring, fans,
etc.
The Power-On Reset (POR) initializes the registers to their default state, causing the bits
to be set HIGH (LED off).
Due to pin limitations, the PCA9533 is not featured with hardware address pins. The
PCA9533/01 and the PCA9533/02 have different fixed I
2
C-bus addresses allowing
operation of both on the same bus.
2. Features
I
4 LED drivers (on, off, flashing at a programmable rate)
I
Two selectable, fully programmable blink rates (frequency and duty cycle) between
0.591 Hz and 152 Hz (1.69 second and 6.58 milliseconds)
I
256 brightness steps
I
Input/outputs not used as LED drivers can be used as regular GPIOs
I
Internal oscillator requires no external components
I
I
2
C-bus interface logic compatible with SMBus
NXP Semiconductors
PCA9533
4-bit I
2
C-bus LED dimmer
I
I
I
I
I
I
I
I
I
I
Internal power-on reset
Noise filter on SCL/SDA inputs
4 open-drain outputs directly drive LEDs to 25 mA
Edge rate control on outputs
No glitch on power-up
Supports hot insertion
Low standby current
Operating power supply voltage range of 2.3 V to 5.5 V
0 Hz to 400 kHz clock frequency
ESD protection exceeds 2000 V HBM per JESD22-A114, 150 V MM per
JESD22-A115 and 1000 V CDM per JESD22-C101
I
Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
I
Packages offered: SO8, TSSOP8 (MSOP8)
3. Ordering information
Table 1.
Ordering information
Package
Name
PCA9533D/01
PCA9533D/02
PCA9533DP/01
PCA9533DP/02
TSSOP8
SO8
Description
plastic small outline package; 8 leads;
body width 3.9 mm
plastic thin shrink small outline package; 8 leads;
body width 3 mm
Version
SOT96-1
SOT505-1
Type number
3.1 Ordering options
Table 2.
Ordering options
Topside mark
P9533/1
P9533/2
P33/1
P33/2
Temperature range
T
amb
=
−40 °C
to +85
°C
T
amb
=
−40 °C
to +85
°C
T
amb
=
−40 °C
to +85
°C
T
amb
=
−40 °C
to +85
°C
Type number
PCA9533D/01
PCA9533D/02
PCA9533DP/01
PCA9533DP/02
PCA9533_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 27 April 2009
2 of 24
NXP Semiconductors
PCA9533
4-bit I
2
C-bus LED dimmer
4. Block diagram
PCA9533
INPUT
REGISTER
I
2
C-BUS
CONTROL
LED SELECT (LSn)
REGISTER
SCL
SDA
INPUT
FILTERS
0
1
V
DD
POWER-ON
RESET
PRESCALER 0
REGISTER
PRESCALER 1
REGISTER
PWM0
REGISTER
PWM1
REGISTER
BLINK0
BLINK1
LEDn
OSCILLATOR
V
SS
002aae626
Remark:
Only one I/O shown for clarity.
Fig 1.
Block diagram of PCA9533
5. Pinning information
5.1 Pinning
PCA9533D/01
PCA9533D/02
LED0
LED1
LED2
V
SS
1
2
3
4
002aae624
PCA9533DP/01
PCA9533DP/02
8
7
6
5
V
DD
SDA
SCL
LED3
LED0
LED1
LED2
V
SS
1
2
3
4
002aae625
8
7
6
5
V
DD
SDA
SCL
LED3
Fig 2.
Pin configuration for SO8
Fig 3.
Pin configuration for TSSOP8
5.2 Pin description
Table 3.
Symbol
LED0
LED1
LED2
V
SS
LED3
Pin description
Pin
1
2
3
4
5
Description
LED driver 0
LED driver 1
LED driver 2
supply ground
LED driver 3
PCA9533_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 27 April 2009
3 of 24
NXP Semiconductors
PCA9533
4-bit I
2
C-bus LED dimmer
Pin description
…continued
Pin
6
7
8
Description
serial clock line
serial data line
supply voltage
Table 3.
Symbol
SCL
SDA
V
DD
6. Functional description
Refer to
Figure 1 “Block diagram of PCA9533”.
6.1 Device address
Following a START condition, the bus master must output the address of the slave it is
accessing. The address of the PCA9533/01 is shown in
Figure 4
and the address of
PCA9533/02 is shown in
Figure 5.
slave address
1
1
0
0
0
1
0
R/W
1
1
slave address
0
0
0
1
1
R/W
002aae627
002aae628
Fig 4.
PCA9533/01 slave address
Fig 5.
PCA9533/02 slave address
The last bit of the address byte defines the operation to be performed. When set to logic 1
a read is selected, while a logic 0 selects a write operation.
6.2 Control register
Following the successful acknowledgement of the slave address, the bus master will send
a byte to the PCA9533, which will be stored in the Control register.
0
0
0
AI
0
B2
B1
B0
Auto-Increment
flag
register address
002aad744
Reset state: 00h
Fig 6.
Control register
The lowest 3 bits are used as a pointer to determine which register will be accessed.
If the Auto-Increment (AI) flag is set, the three low order bits of the Control register are
automatically incremented after a read or write. This allows the user to program the
registers sequentially. The contents of these bits will rollover to ‘000’ after the last register
is accessed.
When Auto-Increment flag is set (AI = 1) and a read sequence is initiated, the sequence
must start by reading a register different from the INPUT register (B2 B1 B0
≠
0 0 0).
Only the 3 least significant bits are affected by the AI flag. Unused bits must be
programmed with zeroes.
PCA9533_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 27 April 2009
4 of 24
NXP Semiconductors
PCA9533
4-bit I
2
C-bus LED dimmer
6.2.1 Control register definition
Table 4.
B2
0
0
0
0
1
1
B1
0
0
1
1
0
0
Register summary
B0
0
1
0
1
0
1
Symbol
INPUT
PSC0
PWM0
PSC1
PWM1
LS0
Access
read only
read/write
read/write
read/write
read/write
read/write
Description
input register
frequency prescaler 0
PWM register 0
frequency prescaler 1
PWM register 1
LED selector
6.3 Register descriptions
6.3.1 INPUT - Input register
The INPUT register reflects the state of the device pins. Writes to this register will be
acknowledged but will have no effect.
Table 5.
Bit
Symbol
Default
INPUT - Input register description
7
-
0
6
-
0
5
-
0
4
-
0
3
LED3
X
2
LED2
X
1
LED1
X
0
LED0
X
Remark:
The default value ‘X’ is determined by the externally applied logic level (normally
logic 1) when used for directly driving LED with pull-up to V
DD
.
6.3.2 PCS0 - Frequency Prescaler 0
PSC0 is used to program the period of the PWM output.
The period of BLINK0 = (PSC0 + 1) / 152.
Table 6.
Bit
Symbol
Default
PSC0 - Frequency Prescaler 0 register description
7
PSC0[7]
0
6
PSC0[6]
0
5
PSC0[5]
0
4
PSC0[4]
0
3
PSC0[3]
0
2
PSC0[2]
0
1
PSC0[1]
0
0
PSC0[0]
0
6.3.3 PWM0 - Pulse Width Modulation 0
The PWM0 register determines the duty cycle of BLINK0. The outputs are LOW (LED on)
when the count is less than the value in PWM0 and HIGH (LED off) when it is greater. If
PWM0 is programmed with 00h, then the PWM0 output is always HIGH (LED off).
The duty cycle of BLINK0 = PWM0 / 256.
Table 7.
Bit
Symbol
Default
PWM0 - Pulse Width Modulation 0 register description
7
PWM0
[7]
1
6
PWM0
[6]
0
5
PWM0
[5]
0
4
PWM0
[4]
0
3
PWM0
[3]
0
2
PWM0
[2]
0
1
PWM0
[1]
0
0
PWM0
[0]
0
PCA9533_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 27 April 2009
5 of 24
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