MAX17120ETJ+
RELIABILITY REPORT
FOR
MAX17120ETJ+
PLASTIC ENCAPSULATED DEVICES
September 4, 2009
MAXIM INTEGRATED PRODUCTS
120 SAN GABRIEL DR.
SUNNYVALE, CA 94086
Approved by
Richard Aburano
Quality Assurance
Manager, Reliability Operations
Maxim Integrated Products. All rights reserved.
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MAX17120ETJ+
Conclusion
The MAX17120ETJ+ successfully meets the quality and reliability standards required of all Maxim products. In addition, Maxim’s
continuous reliability monitoring program ensures that all outgoing product will continue to meet Maxim’s quality and reliability standards.
Table of Contents
I. ........Device Description
II. ........Manufacturing Information
III. .......Packaging Information
.....Attachments
I. Device Description
A. General
The MAX17120 includes three high-voltage, level-shifting scan drivers for TFT panel integrated gate logic. Each scan driver has two channels that
switch complementarily. The scan driver outputs swing from +40V to -30V and can swiftly drive capacitive loads. To save power, the scan driver's
complementary outputs share the charge of their capacitive load before they change states.
V. ........Quality Assurance Information
VI. .......Reliability Evaluation
IV. .......Die Information
The MAX17120 is available in a 32-pin, 5mm x 5mm, thin QFN package with a maximum thickness of 0.8mm for ultra-thin LCD panels.
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MAX17120ETJ+
II. Manufacturing Information
A. Description/Function:
B. Process:
C. Number of Device Transistors:
D. Fabrication Location:
E. Assembly Location:
F. Date of Initial Production:
III. Packaging Information
A. Package Type:
B. Lead Frame:
C. Lead Finish:
D. Die Attach:
E. Bondwire:
F. Mold Material:
G. Assembly Diagram:
H. Flammability Rating:
I. Classification of Moisture Sensitivity per
JEDEC standard J-STD-020-C
J. Single Layer Theta Ja:
K. Single Layer Theta Jc:
L. Multi Layer Theta Ja:
M. Multi Layer Theta Jc:
IV. Die Information
A. Dimensions:
B. Passivation:
C. Interconnect:
D. Backside Metallization:
E. Minimum Metal Width:
F. Minimum Metal Spacing:
G. Bondpad Dimensions:
H. Isolation Dielectric:
I. Die Separation Method:
63 X 86 mils
Si
3
N
4
/SiO
2
(Silicon nitride/ Silicon dioxide)
Al with Ti/TiN Barrier
None
Metal1 = 0.5 / Metal2 = 0.6 / Metal3 = 0.6 microns (as drawn)
Metal1 = 0.45 / Metal2 = 0.5 / Metal3 = 0.6 microns (as drawn)
5 mil. Sq.
SiO
2
Wafer Saw
32-pin TQFN 5x5
Copper
100% matte Tin
Non-conductive
Au (1 mil dia.)
Epoxy with silica filler
#05-9000-3694
Class UL94-V0
Level 1
53.7°C/W
19.9°C/W
40.2°C/W
19.9°C/W
Triple High-Voltage Scan Driver for TFT LCD
S4
2800
California
Thailand
July 25, 2009
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MAX17120ETJ+
V. Quality Assurance Information
A. Quality Assurance Contacts:
Ken Wendel (Director, Reliability Engineering)
Bryan Preeshl (Managing Director of QA)
0.1% for all electrical parameters guaranteed by the Datasheet.
0.1% For all Visual Defects.
< 50 ppm
Mil-Std-105D
B. Outgoing Inspection Level:
C. Observed Outgoing Defect Rate:
D. Sampling Plan:
VI. Reliability Evaluation
A. Accelerated Life Test
The results of the 135°C biased (static) life test are pending. Using these results, the Failure Rate ( ) is calculated as follows:
=
1
MTTF
=
1.83
(Chi square value for MTTF upper limit)
192 x 4340 x 48 x 2
(where 4340 = Temperature Acceleration factor assuming an activation energy of 0.8eV)
-9
= 22.9 x 10
= 22.9 F.I.T. (60% confidence level @ 25°C)
The following failure rate represents data collected from Maxim’s reliability monitor program. Maxim performs quarterly
1000 hour life test monitors on its processes. This data is published in the Product Reliability Report found at http://www.maxim-
ic.com/.
Current monitor data for the S4 Process results in a FIT Rate of 0.28 @ 25C and 4.85 @ 55C (0.8 eV, 60% UCL)
B. Moisture Resistance Tests
The industry standard 85°C/85%RH or HAST testing is monitored per device process once a quarter.
C. E.S.D. and Latch-Up Testing
The PF59 die type has been found to have all pins able to withstand a HBM transient pulse of:
HBM ESD: +/-2500V per JEDEC JESD22-A114
CDM ESD: +/-750V per JESD22-C101
MM ESD: +/-200V per JEDEC JESD22-A115
Latch-Up testing has shown that this device withstands a current of +/-100 mA, 1.5x VCCMax Overvoltage per JESD78.
Maxim Integrated Products. All rights reserved.
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MAX17120ETJ+
Table 1
Reliability Evaluation Test Results
MAX17120ETJ+
TEST ITEM
TEST CONDITION
FAILURE
IDENTIFICATION
SAMPLE SIZE
NUMBER OF
FAILURES
Static Life Test
(Note 1)
Ta = 135°C
Biased
Time = 192 hrs.
Moisture Testing
(Note 2)
85/85
Ta = 85°C
RH = 85%
Biased
Time = 1000hrs.
DC Parameters
& functionality
48
0
DC Parameters
& functionality
77
0
Mechanical Stress
(Note 2)
Temperature
-65°C/150°C
Cycle
1000 Cycles
Method 1010
DC Parameters
& functionality
77
0
Note 1: Life Test Data may represent plastic DIP qualification lots.
Note 2: Generic Package/Process data
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