S29GL064S
64-Mbit (8 Mbyte),
3.0 V, Flash Memory
Distinctive Characteristics
CMOS 3.0 Volt Core with Versatile I/O
Package Options
– 48-pin TSOP
– 56-pin TSOP
– 64-ball Fortified BGA (LAA064 13 mm
11 mm
1.4 mm)
(LAE064 9 mm
9 mm
1.4 mm)
– 48-ball fine-pitch BGA (VBK048 8.15 mm
6.15 mm
1.0 mm)
Temperature Range
– Industrial (
40°C to +85°C)
– Industrial Plus (
40°C to +105°C)
– Automotive, AEC-Q100 Grade 3 (
40°C to +85°C)
– Automotive, AEC-Q100 Grade 2(
40°C to +105°C)
Architectural Advantages
Single Power Supply Operation
Manufactured on 65 nm MirrorBit Process Technology
Secure Silicon
Region
– 128-word/256-byte sector for permanent, secure
identification through an 8-word / 16-byte random
Electronic Serial Number, accessible through a command
sequence
– Programmed and locked at the factory or by the customer
Flexible Sector Architecture
– 64 Mb (uniform sector models): One hundred twenty-eight
32-kword (64-kB) sectors
– 64 Mb (boot sector models): One hundred twenty-seven
32-kword (64-kB) sectors + eight 4kword (8kB) boot
sectors
Automatic Error Checking and Correction (ECC) - internal
hardware ECC with single bit error correction
Enhanced VersatileI/O Control
– All input levels (address, control, and DQ input levels) and
outputs are determined by voltage on V
IO
input. V
IO
range
is 1.65 to V
CC
Compatibility with JEDEC Standards
– Provides pinout and software compatibility for single-power
supply flash, and superior inadvertent write protection
100,000 Erase Cycles per Sector Minimum
20-year Data Retention Typical
Software and Hardware Features
Software Features
– Advanced Sector Protection: offers Persistent Sector
Protection and Password Sector Protection
– Program Suspend and Resume: read other sectors before
programming operation is completed
– Erase Suspend and Resume: read / program other sectors
before an erase operation is completed
– Data# polling and toggle bits provide status
– CFI (Common Flash Interface) compliant: allows host
system to identify and accommodate multiple flash devices
– Unlock Bypass Program command reduces overall
multiple-word programming time
Hardware Features
– WP#/ACC input supports manufacturing programming
operations (when high voltage is applied). Protects first or
last sector regardless of sector protection settings on
uniform sector models
– Hardware reset input (RESET#) resets device
– Ready/Busy# output (RY/BY#) detects program or erase
cycle completion
Performance Characteristics
High Performance
– 70 ns access time
– 8-word / 16-byte page read buffer
– 15 ns page read time
– 128-word / 256-byte write buffer which reduces overall
programming time for multiple-word updates
Low Power Consumption
– 25 mA typical initial read current @ 5 MHz
– 7.5 mA typical page read current @ 33 MHz
– 50 mA typical erase / program current
– 40 µA typical standby mode current
Cypress Semiconductor Corporation
Document Number: 001-98286 Rev. *H
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised August 03, 2018
S29GL064S
General Description
The S29GL-S mid density family of devices are 3.0-volt single-power flash memory manufactured using 65 nm MirrorBit technology.
The S29GL064S is a 64-Mb device organized as 4,194,304 words or 8,388,608 bytes. Depending on the model number, the devices
have 16-bit wide data bus only, or a 16-bit wide data bus that can also function as an 8-bit wide data bus by using the BYTE# input.
The devices can be programmed either in the host system or in standard EPROM programmers.
Access times as fast as 70 ns are available. Note that each access time has a specific operating voltage range (V
CC
) as specified in
the
Product Selector Guide
and
Ordering Information.
Package offerings include 48-pin TSOP, 56-pin TSOP, 48-ball fine-pitch BGA,
and 64-ball Fortified BGA, depending on model number. Each device has separate chip enable (CE#), write enable (WE#) and
output enable (OE#) controls.
Each device requires only a
single 3.0-volt power supply
for both read and write functions. In addition to a V
CC
input, a high-
voltage
accelerated program (ACC)
feature is supported through increased voltage on the WP#/ACC or ACC input. This feature is
intended to facilitate system production.
The device is entirely command set compatible with the
JEDEC single-power-supply flash standard.
Commands are written to
the device using standard microprocessor write timing. Write cycles also internally latch addresses and data needed for the
programming and erase operations.
The
sector erase architecture
allows memory sectors to be erased and reprogrammed without affecting the data contents of other
sectors. The device is fully erased when shipped from the factory.
The
Advanced Sector Protection
features several levels of sector protection, which can disable both the program and erase
operations in certain sectors. Persistent Sector Protection is a method that replaces the previous 12-volt controlled protection
method. Password Sector Protection is a highly sophisticated protection method that requires a password before changes to certain
sectors are permitted.
Device programming and erasure are initiated through command sequences. Once a program or erase operation begins, the host
system need only poll the DQ7 (Data# Polling) or DQ6 (toggle)
status bits
or monitor the
Ready/Busy# (RY/BY#)
output to
determine whether the operation is complete. To facilitate programming, an
Unlock Bypass
mode reduces command sequence
overhead by requiring only two write cycles to program data instead of four.
Hardware data protection
measures include a low V
CC
detector that automatically inhibits write operations during power
transitions. The hardware sector protection feature disables both program and erase operations in any combination of sectors of
memory. This can be achieved in-system or via programming equipment.
The
Erase Suspend / Erase Resume
feature allows the host system to pause an erase operation in a given sector to read or
program any other sector and then complete the erase operation. The
Program Suspend / Program Resume
feature enables the
host system to pause a program operation in a given sector to read any other sector and then complete the program operation.
The
hardware RESET# pin
terminates any operation in progress and resets the device, after which it is then ready for a new
operation. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the
host system to read boot-up firmware from the flash memory device.
The device reduces power consumption in the
standby mode
when it detects specific voltage levels on CE# and RESET#, or when
addresses are stable for a specified period of time.
The
Write Protect (WP#)
feature protects the first or last sector by asserting a logic low on the WP#/ACC pin or WP# pin, depending
on model number. The protected sector is still protected even during accelerated programming.
The
Secure Silicon Region
provides a 128-word / 256-byte area for code or data that can be permanently protected. Once this
sector is protected, no further changes within the sector can occur.
Cypress MirrorBit flash technology combines years of flash memory manufacturing experience to produce the highest levels of
quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via hot-hole assisted
erase. The data is programmed using hot electron injection.
Document Number: 001-98286 Rev. *H
Page 2 of 106
S29GL064S
Contents
1.
2.
3.
4.
5.
6.
6.1
7.
7.1
7.2
7.3
8.
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
8.10
8.11
8.12
8.13
8.14
8.15
8.16
8.17
8.18
8.19
9.
10.
10.1
10.2
10.3
10.4
10.5
Product Selector Guide
............................................... 4
Block Diagram..............................................................
5
Connection Diagrams..................................................
6
Pin Description.............................................................
9
S29GL064S Logical Symbols....................................
10
Ordering Information
................................................. 11
Valid Combinations ...................................................... 12
Other Resources
........................................................
Cypress Flash Memory Roadmap ...............................
Links to Software .........................................................
Links to Application Notes............................................
Device Bus Operations..............................................
Word / Byte Configuration............................................
Requirements for Reading Array Data.........................
Writing Commands / Command Sequences................
Automatic ECC ............................................................
Standby Mode..............................................................
Automatic Sleep Mode.................................................
RESET#: Hardware Reset Pin.....................................
Output Disable Mode ...................................................
Memory Map ................................................................
Autoselect Mode ..........................................................
Advanced Sector Protection ........................................
Lock Register ...............................................................
Persistent Sector Protection ........................................
Password Sector Protection.........................................
Password and Password Protection Mode Lock Bit ....
Persistent Protection Bit Lock (PPB Lock Bit)..............
Secure Silicon Region Flash Memory..........................
Write Protect (WP#/ACC) ............................................
Hardware Data Protection............................................
13
13
13
13
14
14
15
15
16
17
17
17
18
18
19
20
21
22
24
24
24
25
26
26
30
30
30
31
31
31
31
32
32
33
34
36
38
38
10.14 Erase Suspend / Erase Resume Commands.............. 39
10.15 Evaluate Erase Status ................................................. 40
10.16 Continuity Check ......................................................... 40
10.17 Command Definitions .................................................. 42
11. Data Integrity
............................................................... 49
11.1 Erase Endurance .......................................................... 49
11.2 Data Retention .............................................................. 49
12. Status Monitoring
....................................................... 50
12.1 Status Register ............................................................. 50
12.2 Write Operation Status.................................................. 51
12.3 DQ7: Data# Polling ....................................................... 52
12.4 DQ6: Toggle Bit I .......................................................... 54
12.5 DQ2: Toggle Bit II ......................................................... 56
12.6 Reading Toggle Bits DQ6/DQ2..................................... 56
12.7 DQ5: Exceeded Timing Limits ...................................... 56
12.8 DQ3: Sector Erase Timer.............................................. 56
12.9 DQ1: Write-to-Buffer Abort............................................ 57
12.10 RY/BY#: Ready/Busy# ................................................ 57
12.11 Error Types and Clearing Procedures ......................... 57
13.
14.
14.1
14.2
14.3
14.4
Command State Transitions
...................................... 61
Electrical Specifications.............................................
74
Absolute Maximum Ratings .......................................... 74
Latchup Characteristics ................................................ 74
Thermal Resistance ...................................................... 74
Operating Ranges......................................................... 74
15. DC Characteristicst.....................................................
77
15.1 Capacitance Characteristics ......................................... 79
16.
16.1
16.2
16.3
17.
17.1
17.2
17.3
18.
Test Specifications
..................................................... 81
Key to Switching Waveforms ........................................ 81
AC Test Conditions ....................................................... 81
Power-On Reset (POR) and Warm Reset .................... 82
AC Characteristics......................................................
84
Read-Only Operations .................................................. 84
Asynchronous Write Operations ................................... 88
Alternative CE# Controlled Write Operations................ 94
Erase and Programming Performance
..................... 97
Common Flash Memory Interface (CFI)
................... 27
Command Definitions................................................
Reading Array Data .....................................................
Reset Command ..........................................................
Autoselect Command Sequence .................................
Status Register ASO....................................................
Enter / Exit Secure Silicon Region
Command Sequence ...................................................
10.6 ECC Status ASO..........................................................
10.7 Word Program Command Sequence...........................
10.8 Unlock Bypass Command Sequence ..........................
10.9 Write Buffer Programming ...........................................
10.10 Accelerated Program..................................................
10.11 Program Suspend / Program Resume
Command Sequence ...................................................
10.12 Chip Erase Command Sequence ...............................
10.13 Sector Erase Command Sequence ............................
19. Physical Dimensions
.................................................. 99
19.1 TS048—48-Pin Standard
Thin Small Outline Package (TSOP) ............................ 99
19.2 TS056—56-Pin Standard
Thin Small Outline Package (TSOP) .......................... 100
19.3 VBK048—Ball Fine-pitch Ball Grid Array (BGA)
8.15 x 6.15 mm Package ............................................ 101
19.4 LAA064—64-Ball Fortified Ball Grid Array (BGA)
13 x 11 mm Package .................................................. 102
19.5 LAE064—64-Ball Fortified Ball Grid Array (BGA)
9 x 9 mm Package ...................................................... 103
20.
Revision History........................................................
104
Document Number: 001-98286 Rev. *H
Page 3 of 106
S29GL064S
1.
Product Selector Guide
Table 1. Product Selector Guide for Industrial Temperature Range (
40°C to +85°C)
Part Number
Speed Option
Max. Access Time (ns)
Max. CE# Access Time (ns)
Max. Page Access Time (ns)
Max. OE# Access Time (ns)
V
CC
= 2.7–3.6V
V
IO
= 2.7–3.6V
V
IO
= 1.65–3.6V
70
70
15
15
S29GL064S
70
80
80
80
25
25
Table 2. Product Selector Guide for Industrial Plus Temperature Range (
40°C to +105°C)
Part Number
Speed Option
Max. Access Time (ns)
Max. CE# Access Time (ns)
Max. Page Access Time (ns)
Max. OE# Access Time (ns)
V
CC
= 2.7–3.6V
V
IO
= 2.7–3.6V
V
IO
= 1.65–3.6V
80
80
15
15
S29GL064S
80
90
90
90
25
25
Document Number: 001-98286 Rev. *H
Page 4 of 106
S29GL064S
2. Block Diagram
RY/BY#
V
CC
V
SS
Sector Switches
DQ15–DQ0 (A-1)
RESET#
Erase Voltage
Generator
Input / Output
Buffers
WE#
WP#/ACC(1)
BYTE#(2)
State
Control
Command
Register
PGM Voltage
Generator
Chip Enable
Output Enable
Logic
STB
Data
Latch
CE#
OE#
STB
Y-Decoder
Y-Gating
Timer
Address Latch
V
CC
Detector
X-Decoder
Cell Matrix
A21–A0
Notes:
1. Available on separate pins for models 06, 07, V6, V7.
2. Available only on X8/x16 devices.
Document Number: 001-98286 Rev. *H
Page 5 of 106
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