CY62147G/CY621472G
CY62147GE MoBL
®
4-Mbit (256K words × 16-bit) Static RAM
with Error-Correcting Code (ECC)
4-Mbit (256K words × 16-bit) Static RAM with Error-Correcting Code (ECC)
Features
■
■
High speed: 45 ns/55 ns
Ultra-low standby power
❐
Typical standby current: 3.5
A
❐
Maximum standby current: 8.7
A
Embedded ECC for single-bit error correction
[1, 2]
Wide voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V, and 4.5 V
to 5.5 V
1.0-V data retention
TTL-compatible inputs and outputs
Error indication (ERR) pin to indicate 1-bit error detection and
correction
Pb-free 48-ball VFBGA and 44-pin TSOP II packages
Data writes are performed by asserting the Write Enable (WE)
input LOW, while providing the data on I/O
0
through I/O
15
and
address on A
0
through A
17
pins. The Byte High Enable (BHE)
and Byte Low Enable (BLE) inputs control write operations to the
upper and lower bytes of the specified memory location. BHE
controls I/O
8
through I/O
15
and BLE controls I/O
0
through I/O
7
.
Data reads are performed by asserting the Output Enable (OE)
input and providing the required address on the address lines.
Read data is accessible on the I/O lines (I/O
0
through I/O
15
).
Byte accesses can be performed by asserting the required byte
enable signal (BHE or BLE) to read either the upper byte or the
lower byte of data from the specified address location.
All I/Os (I/O
0
through I/O
15
) are placed in a HI-Z state when the
device is deselected (CE HIGH for a single chip enable device
and CE
1
HIGH/CE
2
LOW for a dual chip enable device), or
control signals are de-asserted (OE, BLE, BHE).
The device also has a unique Byte Power down feature, where,
if both the Byte Enables (BHE and BLE) are disabled, the
devices seamlessly switch to standby mode irrespective of the
state of the chip enables, thereby saving power.
On the CY62147GE devices, the detection and correction of a
single-bit error in the accessed location is indicated by the
assertion of the ERR output (ERR = HIGH)
[1]
. See the
Truth
Table – CY62147G/CY62147GE on page 16
for a complete
description of read and write modes.
The logic block diagrams are on page 2.
■
■
■
■
■
■
Functional Description
CY62147G and CY62147GE are high-performance CMOS
low-power (MoBL) SRAM devices with embedded ECC. Both
devices are offered in single and dual chip enable options and in
multiple pin configurations. The CY62147GE device includes an
ERR pin that signals an error-detection and correction event
during a read cycle.
Devices with a single chip enable input are accessed by
asserting the chip enable (CE) input LOW. Dual chip enable
devices are accessed by asserting both chip enable inputs – CE
1
as low and CE
2
as HIGH.
Product Portfolio
Product
[3]
Features and
Options
(see the Pin
Configurations
section)
Power Dissipation
Range
V
CC
Range (V)
Speed (ns)
Operating I
CC
, (mA)
f = f
max
Typ
[4]
Industrial
1.65 V–2.2 V
2.2 V–3.6 V
4.5 V–5.5 V
55
45
15
15
Max
20
20
Standby, I
SB2
(µA)
Typ
[4]
3.5
3.5
Max
10
8.7
CY62147G(E)18 Single or dual
CY62147G(E)30 Chip Enables
CY621472G30
Optional ERR
CY62147G(E)
pin
Notes
1. This device does not support automatic write-back on error detection.
2. SER FIT Rate <0.1 FIT/Mb. Refer
AN88889
for details.
3.
The ERR pin is available only for devices which have ERR option “E” in the ordering code. Refer
Ordering Information on page 17.
4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= 1.8 V (for a V
CC
range of 1.65 V–2.2 V),
V
CC
= 3 V (for V
CC
range of 2.2 V–3.6 V), and V
CC
= 5 V (for V
CC
range of 4.5 V–5.5 V), T
A
= 25 °C.
Cypress Semiconductor Corporation
Document Number: 001-92847 Rev. *K
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised July 13, 2018
CY62147G/CY621472G
CY62147GE MoBL
®
Contents
Pin Configuration – CY62147G ........................................ 4
Pin Configuration – CY62147GE ..................................... 5
Pin Configuration – CY621472G ...................................... 6
Maximum Ratings ............................................................. 7
Operating Range ............................................................... 7
DC Electrical Characteristics .......................................... 7
Capacitance ...................................................................... 9
Thermal Resistance .......................................................... 9
AC Test Loads and Waveforms ....................................... 9
Data Retention Characteristics ..................................... 10
Data Retention Waveform .............................................. 10
AC Switching Characteristics ....................................... 11
Switching Waveforms .................................................... 12
Truth Table – CY62147G/CY62147GE ........................... 16
ERR Output – CY62147GE ............................................. 16
Ordering Information ...................................................... 17
Ordering Code Definitions ......................................... 18
Package Diagrams .......................................................... 19
Acronyms ........................................................................ 20
Document Conventions ................................................. 20
Units of Measure ....................................................... 20
Document History Page ................................................. 21
Sales, Solutions, and Legal Information ...................... 22
Worldwide Sales and Design Support ....................... 22
Products .................................................................... 22
PSoC® Solutions ...................................................... 22
Cypress Developer Community ................................. 22
Technical Support ..................................................... 22
Document Number: 001-92847 Rev. *K
Page 3 of 22
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