AT25SL321
32-Mbit, 1.7V Minimum
SPI Serial Flash Memory with Dual I/O, Quad I/O and QPI Support
Features
Single 1.7V - 2.0V Supply
Serial Peripheral Interface (SPI) and Quad Peripheral Interface (QPI) Compatible
Supports SPI Modes 0 and 3
Supports Dual Output Read and Quad I/O Program and Read
Supports QPI Program and Read
104 MHz* Maximum Operating Frequency
Clock-to-Output (t
V1
) of 6 ns
Up tp 65MB/S continuous data transfer rate
Full Chip Erase
Flexible, Optimized Erase Architecture for Code and Data Storage Applications
0.6 ms Typical Page Program (256 Bytes) Time
60 ms Typical 4-Kbyte Block Erase Time
200 ms Typical 32-Kbyte Block Erase Time
300 ms Typical 64-Kbyte Block Erase Time
Hardware Controlled Locking of Protected Blocks via WP Pin
4K-bit secured One-Time Programmable Security Register
Hardware Write Protection
Serial Flash Discoverable Parameters (SFDP) Register
Flexible Programming
Byte/Page Program (1 to 256 Bytes)
Dual or Quad Input Byte/Page Program (1 to 256 Bytes)
Accelerated programming mode via 9V ACC pin
Erase/Program Suspend and Resume
JEDEC Standard Manufacturer and Device ID Read Methodology
Low Power Dissipation
2µA Deep Power-Down Current (Typical)
10µA Standby current (Typical)
5mA Active Read Current (Typical)
Endurance: 100,000 program/erase cycles (4KB, 32KB or 64KB blocks)
Data Retention: 20 Years
Industrial Temperature Range: -40°C to +85°C
Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options
8-lead SOIC (208-mil)
8-pad DFN (6 x 5 x 0.6 mm)
24-ball Ball Grid Array (BGA)
8 and 10-ball WLCSP, die Ball Grid Array (dBGA)
8-pad USON(3 x 4 x 0.55mm)
Die in Wafer Form
DS-25SL321–112F–3/2017
1.
Introduction
The Adesto
®
AT25SL321 is a serial interface Flash memory device designed for use in a wide variety of high-volume
consumer based applications in which program code is shadowed from Flash memory into embedded or external RAM
for execution. The flexible erase architecture of the AT25SL321 is ideal for data storage as well, eliminating the need for
additional data storage devices.
The erase block sizes of the AT25SL321 have been optimized to meet the needs of today's code and data storage
applications. By optimizing the size of the erase blocks, the memory space can be used much more efficiently. Because
certain code modules and data storage segments must reside by themselves in their own erase regions, the wasted and
unused memory space that occurs with large block erase Flash memory devices can be greatly reduced. This increased
memory space efficiency allows additional code routines and data storage segments to be added while still maintaining
the same overall device density.
SPI clock frequencies of up to 104MHz* are supported allowing equivalent clock rates of 266MHz for Dual Output and
532MHz for Quad Output when using the QPI and Fast Read Dual/Quad I/O instructions.The AT25SL321 array is
organized into 65,536 programmable pages of 256-bytes each. Up to 256 bytes can be programmed at a time using the
Page Program instructions. Pages can be erased 4KB Block, 32KB Block, 64KB Block or the entire chip.
The devices operate on a single 1.7V to 1.95V power supply with current consumption as low as 5mA active and 2
µ
A for
Deep Power Down. All devices offered in space-saving packages. The device supports JEDEC standard manufacturer
and device identification with a 4K-bit Secured OTP.
*Contact Adesto for availability of 133MHz operating frequency.
AT25SL321
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2.
Pinouts and Pin Descriptions
The following figures show the available package types.
Figure 1-1. 8-SOIC (Top View)
CS
(IO
1
)
(IO
2
)
GND
1
2
3
4
8
7
6
5
VCC
HOLD OR RESET (IO
3
)
SCK
SI (IO
0
)
Figure 1-2. 8-UDFN (Top View)
CS
SO (IO
1
)
WP (IO
2
)
GND
1
2
3
4
8
7
6
5
VCC
HOLD (IO
3
)
SCK
SI (IO
0
)
Figure 1-3. 24-dBGA (Top View)
Figure 1-4. 8-WLCSP (Bottom View)
CS
Vcc
I/O
1
(SO) I/O
3
(HOLD)
I/O
2
(WP)
SCK
GND
I/O
0
(SI)
Figure 1-5. 10-WLCSP (Bottom View)
Figure 1-6. 8-pad USON (Bottom View)
GND
CS
GND
I/O
1
(SO)
I/O
0
(SI)
I/O
2
(WP)
SCK
I/O
3
(HOLD)
Vcc
SI (IO
0
)
SCK
HOLD (IO
3
)
VCC
WP (IO
2
)
SO (IO
1
)
CS
*Final package outline drawing to be confirmed.
AT25SL321
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3
During all operations,
V
CC
must be held stable and within the specified valid range:
V
CC
(min) to
V
CC
(max).
All of the input and output signals must be held high or low (according to voltages of VIH, VOH, VIL or VOL.
Table 1-1.
Symbol
Pin Descriptions
Name and Function
CHIP SELECT
Asserted
State
Type
CS
When this input signal is high, the device is deselected and serial data output pins are at
high impedance. Unless an internal program, erase or write status register cycle is in
progress, the device will be in the standby power mode (this is not the deep power down
mode). Driving Chip Select (CS) low enables the device, placing it in the active power
mode. After power-up, a falling edge on Chip Select (CS) is required prior to the start of
any instruction.
SERIAL CLOCK
Low
Input
SCK
This input signal provides the timing for the serial interface. Instructions, addresses, or
data present at serial data input are latched on the rising edge of Serial Clock (SCK).
Data are shifted out on the falling edge of the Serial Clock (SCK).
SERIAL INPUT
-
Input
The SI pin is used to shift data into the device. The SI pin is used for all data input
including command and address sequences. Data on the SI pin is always latched in on
the rising edge of SCK.
SI (I/O
0
)
With the Dual-Output and Quad-Output Read commands, the SI Pin becomes an output
pin (I/O
0
) in conjunction with other pins to allow two or four bits of data on (I/O
3-0
) to be
clocked in on every falling edge of SCK
To maintain consistency with the SPI nomenclature, the SI (I/O
0
) pin is referenced as the
SI pin unless specifically addressing the Dual-I/O and Quad-I/O modes in which case it is
referenced as I/O
0.
Data present on the SI pin is ignored whenever the device is deselected (CS is
deasserted).
SERIAL OUTPUT
-
Input/Output
The SO pin is used to shift data out from the device. Data on the SO pin is always
clocked out on the falling edge of SCK.
SO (I/O
1
)
With the Dual-Output Read commands, the SO Pin remains an output pin (I/O0) in
conjunction with other pins to allow two bits of data on (I/O
1-0
) to be clocked in on every
falling edge of SCK
To maintain consistency with the SPI nomenclature, the SO (I/O
1
) pin is referenced as
the SO pin unless specifically addressing the Dual-I/O modes in which case it is
referenced as I/O
1.
The SO pin is in a high-impedance state whenever the device is
deselected (CS is deasserted).
-
Input/Output
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Table 1-1.
Symbol
Pin Descriptions (Continued)
Name and Function
WRITE PROTECT
Asserted
State
Type
WP (I/O
2
)
The Write Protect (WP) pin can be used to protect the Status Register against data
modification. The WP pin is active low. When the QE bit of Status Register-2 is set for Quad
I/O, the WP pin (Hardware Write Protect) function is not available since this pin is used for IO
2
.
See figures 1-1, 1-2, and 1-3 for the pin configuration of Quad I/O and QPI operation.
ACCELERATED PROGRAMMING
-
Input/Output
The device offers accelerated program operations through the ACC function. This
function is primarily intended to allow faster manufacturing throughput at the factory.
If the system asserts V
HH
on this pin, the device uses the higher voltage on the pin to
reduce the time required for program operations. Removing V
HH
from the ACC pin
returns the device to normal operation.
Note that the ACC pin must not be at V
HH
for operations other than accelerated
programming, or device damage may result. In addition, the ACC pin must not be left
floating or unconnected; inconsistent behavior of the device may result. The ACC
function is only available during standard SPI Mode.
HOLD
ACC
The HOLD pin is used to pause a serial sequence of the SPI flash memory without
resetting the clocking sequence. To enable the HOLD mode, the CS must be in low state.
The HOLD mode effects on with the falling edge of the HOLD signal with CLK being low.
The HOLD mode ends on the rising edge of HOLD signal with SCK being low.
HOLD
(I/O
3
)
In other words, HOLD mode can't be entered unless SCK is low at the falling edge of the
HOLD signal. And HOLD mode can't be exited unless SCK is low at the rising edge of the
HOLD signal.
If CS is driven high during a HOLD condition, it resets the internal logic of the device. As
long as HOLD signal is low, the memory remains in the HOLD condition. To re-work
communication with the device, HOLD must go high, and CS must go low. See
Figure
8.11
for HOLD timing.
-
Input/Output
V
CC
DEVICE POWER SUPPLY:
V
CC
is the supply voltage. It is the single voltage used for all
device functions including read, program, and erase.
The V
CC
pin is used to supply the
source voltage to the device. Operations at invalid V
CC
voltages may produce spurious results
and should not be attempted.
GROUND:
V
SS
is the reference for the
V
CC
supply voltage.
The ground reference for the
power supply. GND should be connected to the system ground.
-
Power
GND
-
Power
AT25SL321
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