GS81314LD18GK-133 datasheet, PDF

Datasheet> All Categories > semiconductor> Memory IC> Static random access memory> GS81314LD18GK-133

GS81314LD18GK-133: DescriptionStatic random access memory 1.2/1.25V 8M x 18 144M; Categorysemiconductor Memory IC Static random access memory; File Size395KB，40 Pages; ManufacturerGSI Technology; Websitehttp://www.gsitechnology.com/; Environmental Compliance

Download Datasheet Parametric Compare View All

GS81314LD18GK-133 Online Shopping

Suppliers	Part Number	Price	MOQ	In stock
	GS81314LD18GK-133	-	-	View	Buy Now

GS81314LD18GK-133 Overview

Static random access memory 1.2/1.25V 8M x 18 144M

GS81314LD18GK-133 Parametric

Parameter Name	Attribute value
Maker	GSI Technology
Product Category	static random access memory
storage	144 Mbit
organize	8 M x 18
maximum clock frequency	1.333 GHz
Interface Type	Parallel
Supply voltage - max.	1.35 V
Supply voltage - min.	1.2 V
Supply current—max.	2.7 A
Minimum operating temperature	0 C
Maximum operating temperature	+ 85 C
Installation style	SMD/SMT
Package/box	BGA-260
Encapsulation	Tray
storage type	QDR_IVe
series	GS81314LD18GK
type	SigmaQuad-IVe B4
humidity sensitivity	Yes
Factory packaging quantity	10

Preview

Download Datasheet

View All

GS81314LD18/36GK-133/120/106

260-Pin BGA

Com & Ind Temp

HSTL I/O

Features

•

4Mb x 36 and 8Mb x 18 organizations available

Organized as 8 logical memory banks

1333 MHz maximum operating frequency

1.333 BT/s peak transaction rate (in billions per second)

192 Gb/s peak data bandwidth (in x36 devices)

Separate I/O DDR Data Buses

Non-multiplexed SDR Address Bus

One operation - Read or Write - per clock cycle

Certain address/bank restrictions on Read and Write ops

Burst of 4 Read and Write operations

6 cycle Read Latency

On-chip ECC with virtually zero SER

Loopback signal timing training capability

1.25V ~ 1.3V nominal core voltage

1.2V ~ 1.3V HSTL I/O interface

Configuration registers

Configurable ODT (on-die termination)

ZQ pin for programmable driver impedance

ZT pin for programmable ODT impedance

IEEE 1149.1 JTAG-compliant Boundary Scan

260-pin, 14 mm x 22 mm, 1 mm ball pitch, 6/6 RoHS-

compliant BGA package

144Mb SigmaQuad-IVe™

Burst of 4 Multi-Bank ECCRAM™

Clocking and Addressing Schemes

Up to 1333 MHz

1.25V ~ 1.3V V

1.2V ~ 1.3V V

DDQ

The GS81314LD18/36GK SigmaQuad-IVe ECCRAMs are

synchronous devices. They employ three pairs of positive and

negative input clocks; one pair of master clocks, CK and CK,

and two pairs of write data clocks, KD[1:0] and KD[1:0]. All

six input clocks are single-ended; that is, each is received by a

dedicated input buffer.

CK and CK are used to latch address and control inputs, and to

control all output timing. KD[1:0] and KD[1:0] are used solely

to latch data inputs.

Each internal read and write operation in a SigmaQuad-IVe B4

ECCRAM is four times wider than the device I/O bus. An

input data bus de-multiplexer is used to accumulate incoming

data before it is simultaneously written to the memory array.

An output data multiplexer is used to capture the data produced

from a single memory array read and then route it to the

appropriate output drivers as needed. Therefore, the address

field of a SigmaQuad-IVe B4 ECCRAM is always two address

pins less than the advertised index depth (e.g. the 8M x 18 has

2M addressable index).

On-Chip Error Correction Code

GSI's ECCRAMs implement an ECC algorithm that detects

and corrects all single-bit memory errors, including those

induced by SER events such as cosmic rays, alpha particles,

etc. The resulting Soft Error Rate of these devices is

anticipated to be <0.002 FITs/Mb — a 5-order-of-magnitude

improvement over comparable SRAMs with no on-chip ECC,

which typically have an SER of 200 FITs/Mb or more.

All quoted SER values are at sea level in New York City.

SigmaQuad-IVe™ Family Overview

SigmaQuad-IVe ECCRAMs are the Separate I/O half of the

SigmaQuad-IVe/SigmaDDR-IVe family of high performance

ECCRAMs. Although similar to GSI's third generation of

networking SRAMs (the SigmaQuad-IIIe/SigmaDDR-IIIe

family), these fourth generation devices offer several new

features that help enable significantly higher performance.

Parameter Synopsis

Speed Grade

-133

-120

-106

Max Operating Frequency

1333 MHz

1200 MHz

1066 MHz

Read Latency

6 cycles

1.2V to 1.35V

Rev: 1.10 12/2017

1/40

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS81314LD18GK-133 Related Products

	GS81314LD18GK-133	GS81314LD18GK-106I	GS81314LD18GK-133I	GS81314LD36GK-120	GS81314LD36GK-106	GS81314LD36GK-133I	GS81314LD36GK-133	GS81314LD18GK-120I	GS81314LD36GK-120I	GS81314LD36GK-106I
Description	Static random access memory 1.2/1.25V 8M x 18 144M	SRAM 1.2/1.25V 8M x 18 144M	SRAM 1.2/1.25V 8M x 18 144M	SRAM 1.2/1.25V 4M x 36 144M	SRAM 1.2/1.25V 4M x 36 144M	SRAM 1.2/1.25V 4M x 36 144M	SRAM 1.2/1.25V 4M x 36 144M	SRAM 1.2/1.25V 8M x 18 144M	Static random access memory 1.2/1.25V 4M x 36 144M	Static random access memory 1.2/1.25V 4M x 36 144M
Product Category	static random access memory	SRAM	SRAM	SRAM	SRAM	SRAM	SRAM	SRAM	static random access memory	static random access memory
Interface Type	Parallel	Parallel	Parallel	Parallel	Parallel	Parallel	Parallel	Parallel	Parallel	Parallel
Product Attribute	-	Attribute Value	Attribute Value	Attribute Value	Attribute Value	Attribute Value	Attribute Value	Attribute Value	-	-
Manufacturer	-	GSI Technology	GSI Technology	GSI Technology	GSI Technology	GSI Technology	GSI Technology	GSI Technology	-	-
RoHS	-	Details	Details	Details	Details	Details	Details	Details	-	-
Memory Size	-	144 Mbit	144 Mbit	144 Mbit	144 Mbit	144 Mbit	144 Mbit	144 Mbit	-	-
Organization	-	8 M x 18	8 M x 18	4 M x 36	4 M x 36	4 M x 36	4 M x 36	8 M x 18	-	-
Maximum Clock Frequency	-	1.066 GHz	1.333 GHz	1.2 GHz	1.066 GHz	1.333 GHz	1.333 GHz	1.2 GHz	-	-
Supply Voltage - Max	-	1.35 V	1.35 V	1.35 V	1.35 V	1.35 V	1.35 V	1.35 V	-	-
Supply Voltage - Min	-	1.2 V	1.2 V	1.2 V	1.2 V	1.2 V	1.2 V	1.2 V	-	-
Supply Current - Max	-	2.3 A	2.7 A	3.2 A	3 A	3.4 A	3.4 A	2.5 A	-	-
Minimum Operating Temperature	-	- 40 C	- 40 C	0 C	0 C	- 40 C	0 C	- 40 C	-	-
Maximum Operating Temperature	-	+ 100 C	+ 100 C	+ 85 C	+ 85 C	+ 100 C	+ 85 C	+ 100 C	-	-
Mounting Style	-	SMD/SMT	SMD/SMT	SMD/SMT	SMD/SMT	SMD/SMT	SMD/SMT	SMD/SMT	-	-
Package / Case	-	BGA-260	BGA-260	BGA-260	BGA-260	BGA-260	BGA-260	BGA-260	-	-
Packaging	-	Tray	Tray	Tray	Tray	Tray	Tray	Tray	-	-
Memory Type	-	QDR_IVe	QDR_IVe	QDR-IVe	QDR-IVe	QDR-IVe	QDR-IVe	QDR_IVe	-	-
Type	-	SigmaQuad-IVe B4	SigmaQuad-IVe B4	SigmaQuad-IVe B4	SigmaQuad-IVe B4	SigmaQuad-IVe B4	SigmaQuad-IVe B4	SigmaQuad-IVe B4	-	-
Moisture Sensitive	-	Yes	Yes	Yes	Yes	Yes	Yes	Yes	-	-
Factory Pack Quantity	-	10	10	10	10	10	10	10	-	-

Recommended Resources

Class S power amplifier 01

DC motor equivalent circuit

Flip-flop circuit

Rice shed humidity indicator

AC peak clipping circuit composed of CW117

Computer motherboard circuit diagram 440GX_32

PLC clock and time control: In automatic control, clock and time control are often used. For example, the automatic bell ringing at the beginning and end of school and the automatic control equipment are controlled according to ...; frozenviolet Industrial Control Electronics

How to connect two CMOS sensors to the DSP YCbCr bus: How to connect two CMOS sensors to the DSP YCbCr bus? I have never used it before, so I would like to ask you. I am currently using the TI DM644X (ARM+DSP) platform. The original reference design of Y...; mcuer Embedded System

AD9852 Arbitrary Signal Generator Based on MSP430: [i=s]This post was last edited by paulhyde on 2014-9-15 09:17[/i] Has anyone used DDS chip to make an arbitrary signal generator? Please give me some advice and information. Thanks. My email address i...; zipl1985 Electronics Design Contest

The callback function of SetTimer in WinCE stream driver is not executed: In WinCE stream driver, a delay of a certain time is required, but Sleep is not wanted, which will also delay the return of the driver. SetTimer is used, and the output shows that SetTimer is obviousl...; zzy360 Embedded System

Comparison of the performance of Keil, IAR and GCC compilers: Dhrystone test of AT91SAM9261...; fish001 Embedded System

Serial communication problem, very strange: The UTU2440 development board receives the data sent by the computer serial port. It is normal. The computer receives the data sent by the working board. However, the data sent by the working board is...; BlueSummer Embedded System

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components