GS84018/32/36CGT-250/200/166/150
TQFP
Commercial Temp
Industrial Temp
Features
• FT pin for user-configurable flow through or pipelined
operation
• Single Cycle Deselect (SCD) operation
• 3.3 V ±10% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipelined mode
• Byte Write (BW) and/or Global Write (GW) operation
• Common data inputs and data outputs
• Clock control, registered, address, data, and control
• Internal self-timed write cycle
• Automatic power-down for portable applications
• RoHS-compliant 100-lead TQFP package
256K x 18, 128K x 32, 128K x 36
4Mb Sync Burst SRAMs
250 MHz–150 MHz
3.3 V V
DD
3.3 V and 2.5 V I/O
counter may be configured to count in either linear or
interleave order with the Linear Burst Order (LBO) input. The
burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by
the user via the FT mode pin/bump (pin 14 in the TQFP and
bump 5R in the BGA). Holding the FT mode pin/bump low
places the RAM in Flow Through mode, causing output data to
bypass the Data Output Register. Holding FT high places the
RAM in Pipelined mode, activating the rising-edge-triggered
Data Output Register.
SCD Pipelined Reads
The GS84018/32/36CGT is an SCD (Single Cycle Deselect)
pipelined synchronous SRAM. DCD (Dual Cycle Deselect)
versions are also available. SCD SRAMs pipeline deselect
commands one stage less than read commands. SCD RAMs
begin turning off their outputs immediately after the deselect
command has been captured in the input registers.
Byte Write and Global Write
Byte write operation is performed by using byte write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS84018/32/36CGT operates on a 3.3 V power supply
and all inputs/outputs are 3.3 V- and 2.5 V-compatible.
Separate output power (V
DDQ
) pins are used to de-couple
output noise from the internal circuit.
Functional Description
Applications
The GS84018/32/36CGT is a 4,718,592-bit (4,194,304-bit for
x32 version) high performance synchronous SRAM with a 2-
bit burst address counter. Although of a type originally
developed for Level 2 Cache applications supporting high
performance CPUs, the device now finds application in
synchronous SRAM applications ranging from DSP main store
to networking chip set support. The GS84018/32/36CGT is
available in a JEDEC standard 100-lead TQFP package.
Controls
Addresses, data I/Os, chip enables (E
1
, E
2
, E
3
), address burst
control inputs (ADSP, ADSC, ADV), and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
cycles can be initiated with either ADSP or ADSC inputs. In
Burst mode, subsequent burst addresses are generated
internally and are controlled by ADV. The burst address
Parameter Synopsis
-250
Pipeline
3-1-1-1
t
KQ
tCycle
Curr (x18)
Curr (x32/x36)
t
KQ
tCycle
Curr (x18)
Curr (x32/x36)
2.5
4.0
195
225
5.5
5.5
160
180
-200
3.0
5.0
170
195
6.5
6.5
140
160
-166
3.0
5.0
160
185
6.5
6.5
135
155
-150
3.8
6.7
140
160
7.5
7.5
128
145
Unit
ns
ns
mA
mA
ns
ns
mA
mA
Flow Through
2-1-1-1
Rev: 1.01a 6/2017
1/22
© 2014, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS84018/32/36CGT-250/200/166/150
TQFP Pin Description
Symbol
A
0
, A
1
A
B
A
B
B
B
C
B
D
BW
CK
GW
E
1
, E
3
E
2
G
ADV
ADSP, ADSC
DQ
A
DQ
B
DQ
DQ
D
DQP
A
DQP
B
DQP
C
DQP
D
ZZ
FT
LBO
V
DD
V
SS
V
DDQ
NC
Type
I
I
In
In
In
In
I
I
I
I
I
I
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
I
-
Description
Address field LSBs and Address Counter preset Inputs
Address Inputs
Byte Write signal for data inputs DQ
A
; active low
Byte Write signal for data inputs DQ
B
; active low
Byte Write signal for data inputs DQ
C
; active low
Byte Write signal for data inputs DQ
D
; active low
Byte Write—Writes all enabled bytes; active low
Clock Input Signal; active high
Global Write Enable—Writes all bytes; active low
Chip Enable; active low
Chip Enable; active high
Output Enable; active low
Burst address counter advance enable; active low
Address Strobe (Processor, Cache Controller); active low
Byte A Data Input and Output pins
Byte B Data Input and Output pins
Byte C Data Input and Output pins
Byte D Data Input and Output pins
9th Data I/O Pin; Byte A
9th Data I/O Pin; Byte B
9th Data I/O Pin; Byte C
9th Data I/O Pin; Byte D
Sleep Mode control; active high
Flow Through or Pipeline mode; active low
Linear Burst Order mode; active low
Core power supply
I/O and Core Ground
Output driver power supply
No Connect
Rev: 1.01a 6/2017
5/22
© 2014, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Analogue and Mixed Signal
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