S71GS128NB0BFWAK0 datasheet, PDF

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S71GS128NB0BFWAK0: Description128N based MCPs; Categorystorage storage; File Size2MB，195 Pages; ManufacturerSPANSION; Websitehttp://www.spansion.com/; Environmental Compliance

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S71GS128NB0BFWAK0 Overview

128N based MCPs

S71GS128NB0BFWAK0 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	SPANSION
Parts packaging code	BGA
package instruction	8 X 11.60 MM, 1.20 MM HEIGHT, LEAD FREE, FBGA-84
Contacts	84
Reach Compliance Code	unknow
JESD-30 code	R-PBGA-B84
JESD-609 code	e1
length	11.6 mm
memory density	134217728 bi
Memory IC Type	MEMORY CIRCUIT
memory width	16
Humidity sensitivity level	3
Number of functions	1
Number of terminals	84
word count	8388608 words
character code	8000000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-25 °C
organize	8MX16
Package body material	PLASTIC/EPOXY
encapsulated code	TFBGA
Package shape	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	260
Certification status	Not Qualified
Maximum seat height	1.2 mm
Maximum supply voltage (Vsup)	3.1 V
Minimum supply voltage (Vsup)	2.7 V
Nominal supply voltage (Vsup)	3 V
surface mount	YES
technology	CMOS
Temperature level	OTHER
Terminal surface	Tin/Silver/Copper (Sn96.5Ag3.0Cu0.5)
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	40
width	8 mm

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S71GS256/128N based MCPs

Stacked Multi-Chip Product (MCP)

256/128 Megabit (16/8M x 16-bit) CMOS 3.0 Volt V

and

1.8 V V

MirrorBit

Uniform Sector Page-mode Flash

Memory with 64/32 Megabit (4/2M x 16-bit) 1.8V pSRAM

Data Sheet

ADVANCE

INFORMATION

Distinctive Characteristics

MCP Features

■

Power supply voltage

— Flash Memory

: 2.7V to 3.1V

: 1.65V to 1.95V

— pSRAM

: 1.7 V to 1.95 V

High Performance

■

110 ns access time

■

30 ns page read times

■

Packages:

— 8.0x11.6x1.2 mm FBGA (TLA084)

■

Operating Temperature

— -25°C to +85°C (Wireless)

General Description

The S71GS Series is a product line of stacked Multi-chip Product (MCP) packages

and consists of

■

One S29GL Flash memory die with 1.8 V V

■

one 1.8 V pSRAM (Note)

Note:

Burst mode features of the pSRAM in the S71GS family of MCPs is not avail-

able. This MCP uses the page mode operation which utilizes the page mode Flash

and page mode feature-set of the pSRAM.

Publication Number

S71GS256/128N_00

Revision

Amendment

Issue Date

December 17, 2004

This document contains information on a product under development at Spansion, LLC. The information is intended to help you evaluate this product. Do not design in

this product without contacting the factory. Spansion reserves the right to change or discontinue work on this proposed product without notice.

A d v a n c e

I n f o r m a t i o n

S71GS256/128N based MCPs

General Description . . . . . . . . . . . . . . . . . . . . . . . . 1

Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 2

MCP Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . 7

Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 9

Input/Output Descriptions . . . . . . . . . . . . . . . . . . . 11

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 13

Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . 15

Low VCC Write Inhibit ................................................................................61

Write Pulse “Glitch” Protection ................................................................ 61

Logical Inhibit .................................................................................................... 61

Power-Up Write Inhibit ................................................................................61

Common Flash Memory Interface (CFI) . . . . . . . 61

Table 8. CFI Query Identification String ................................

Table 9. System Interface String..........................................

Table 10. Device Geometry Definition ...................................

Table 11. Primary Vendor-Specific Extended Query ................

Command Definitions . . . . . . . . . . . . . . . . . . . . . . 65

Reading Array Data ...........................................................................................66

Reset Command .................................................................................................66

Autoselect Command Sequence ................................................................... 66

Enter Secured Silicon Sector/Exit Secured Silicon

Sector Command Sequence ............................................................................ 67

Word Program Command Sequence .......................................................... 67

Unlock Bypass Command Sequence ........................................................68

Write Buffer Programming .........................................................................68

Accelerated Program ....................................................................................69

Figure 1. Write Buffer Programming Operation....................... 70

Figure 2. Program Operation ............................................... 71

S29GLxxxN MirrorBit

Flash Family

General Description . . . . . . . . . . . . . . . . . . . . . . . 17

Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 19

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

S29GL512N ....................................................................................................... 22

S29GL256N ...................................................................................................... 22

S29GL128N ...................................................................................................... 22

Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 23

Table 1. Device Bus Operations ........................................... 23

Program Suspend/Program Resume Command Sequence ..................... 71

Figure 3. Program Suspend/Program Resume ........................ 72

VersatileIO

) Control .............................................................................23

Requirements for Reading Array Data .........................................................23

Page Mode Read ............................................................................................. 24

Writing Commands/Command Sequences ................................................ 24

Write Buffer .................................................................................................... 24

Accelerated Program Operation .............................................................. 24

Autoselect Functions .....................................................................................25

Standby Mode .......................................................................................................25

Automatic Sleep Mode ......................................................................................25

RESET#: Hardware Reset Pin .........................................................................25

Output Disable Mode ....................................................................................... 26

Table 2. Sector Address Table–S29GL512N ........................... 26

Table 3. Sector Address Table–S29GL256N ........................... 41

Table 4. Sector Address Table–S29GL128N ........................... 48

Chip Erase Command Sequence ................................................................... 72

Sector Erase Command Sequence .................................................................73

Figure 4. Erase Operation ................................................... 74

Erase Suspend/Erase Resume Commands .................................................. 74

Lock Register Command Set Definitions .................................................... 75

Password Protection Command Set Definitions ...................................... 75

Non-Volatile Sector Protection Command Set Definitions .................. 77

Global Volatile Sector Protection Freeze Command Set ...................... 77

Volatile Sector Protection Command Set .................................................. 78

Secured Silicon Sector Entry Command ..................................................... 79

Secured Silicon Sector Exit Command ........................................................ 79

Command Definitions ....................................................................................... 80

Table 12. S29GL512N, S29GL256N, S29GL128N Command

Definitions, x16 .................................................................80

Autoselect Mode .................................................................................................52

Table 5. Autoselect Codes, (High Voltage Method) ................ 53

Write Operation Status ................................................................................... 83

DQ7: Data# Polling ........................................................................................... 83

Figure 5. Data# Polling Algorithm ........................................ 84

Sector Protection ................................................................................................53

Persistent Sector Protection .......................................................................53

Password Sector Protection ........................................................................53

WP# Hardware Protection .........................................................................53

Selecting a Sector Protection Mode .........................................................53

Advanced Sector Protection ...........................................................................54

Lock Register ........................................................................................................54

Table 6. Lock Register ........................................................ 55

RY/BY#: Ready/Busy# .......................................................................................84

DQ6: Toggle Bit I ............................................................................................... 85

Figure 6. Toggle Bit Algorithm ............................................. 86

DQ2: Toggle Bit II ..............................................................................................86

Reading Toggle Bits DQ6/DQ2 ..................................................................... 87

DQ5: Exceeded Timing Limits ........................................................................ 87

DQ3: Sector Erase Timer ................................................................................ 87

DQ1: Write-to-Buffer Abort ...........................................................................88

Table 13. Write Operation Status .........................................88

Persistent Sector Protection ...........................................................................55

Dynamic Protection Bit (DYB) ...................................................................55

Persistent Protection Bit (PPB) ..................................................................56

Persistent Protection Bit Lock (PPB Lock Bit) ......................................56

Table 7. Sector Protection Schemes ..................................... 57

Absolute Maximum Ratings . . . . . . . . . . . . . . . . 89

Figure 7. .......................................................................... 89

Figure 8. Maximum Positive

Overshoot Waveform.......................................................... 89

Persistent Protection Mode Lock Bit ...........................................................57

Password Sector Protection ........................................................................... 58

Password and Password Protection Mode Lock Bit ............................... 58

64-bit Password ...................................................................................................59

Persistent Protection Bit Lock (PPB Lock Bit) ...........................................59

Secured Silicon Sector Flash Memory Region ............................................59

Write Protect (WP#) ........................................................................................ 61

Hardware Data Protection .............................................................................. 61

Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . 89

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 90

Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . .91

Figure 9. Test Setup........................................................... 91

Table 14. Test Specifications ...............................................91

Key to Switching Waveforms . . . . . . . . . . . . . . . . 91

Figure 10. Input Waveforms and Measurement Levels ............ 91

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 92

December 17, 2004 S71GS256/128N_00_A0

A d v a n c e

I n f o r m a t i o n

Read-Only Operations–S29GL128N, S29GL256N, S29GL512N .......... 92

Figure 11. Read Operation Timings....................................... 93

Figure 12. Page Read Timings.............................................. 93

Output Impedance (BCR[5:4]): Default = Outputs Use Full Drive

Strength ............................................................................................................120

Table 20. Output Impedance ............................................. 120

Hardware Reset (RESET#) .............................................................................. 94

Figure 13. Reset Timings..................................................... 94

Erase and Program Operations–S29GL128N,

S29GL256N, S29GL512N ...................................................................................95

Figure 14. Program Operation Timings .................................. 96

Figure 15. Accelerated Program Timing Diagram .................... 96

Figure 16. Chip/Sector Erase Operation Timings..................... 97

Figure 17. Data# Polling Timings

(During Embedded Algorithms) ............................................ 98

Figure 18. Toggle Bit Timings (During Embedded Algorithms) .. 99

Figure 19. DQ2 vs. DQ6 ...................................................... 99

WAIT Configuration (BCR[8]): Default = WAIT Transitions One

Clock Before Data Valid/Invalid ...............................................................120

WAIT Polarity (BCR[10]): Default = WAIT Active HIGH ...............120

Figure 33. WAIT Configuration (BCR[8] = 0) ....................... 120

Figure 34. WAIT Configuration (BCR[8] = 1) ....................... 121

Figure 35. WAIT Configuration During Burst Operation.......... 121

Latency Counter (BCR[13:11]): Default = Three-Clock Latency ......121

Table 21. Variable Latency Configuration Codes ................... 121

Figure 36. Latency Counter (Variable Initial Latency, No Refresh

Collision) ........................................................................ 122

Alternate CE# Controlled Erase and Program Operations-

S29GL128N, S29GL256N, S29GL512N ........................................................100

Figure 20. Alternate CE# Controlled Write (Erase/

Program) Operation Timings.............................................. 101

Operating Mode (BCR[15]): Default = Asynchronous Operation .122

Refresh Configuration Register .....................................................................122

Table 22. Refresh Configuration Register Mapping ................ 123

Partial Array Refresh (RCR[2:0]): Default = Full Array Refresh .... 123

Table 23. 128Mb Address Patterns for PAR (RCR[4] = 1) ....... 123

Table 24. 64Mb Address Patterns for PAR (RCR[4] = 1) ........ 124

Table 25. 32Mb Address Patterns for PAR (RCR[4] = 1) ........ 124

Erase And Programming Performance . . . . . . 102

TSOP Pin and BGA Package Capacitance . . . . 102

CellularRAM Type 2

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

General Description . . . . . . . . . . . . . . . . . . . . . . 103

Figure 21. Functional Block Diagram................................... 104

Table 15. Signal Descriptions .............................................105

Table 16. Bus Operations—Asynchronous Mode ....................106

Table 17. Bus Operations—Burst Mode ................................107

Deep Power-Down (RCR[4]): Default = DPD Disabled ..................124

Temperature Compensated Refresh (RCR[6:5]): Default = +85ºC Op-

eration ..............................................................................................................124

Page Mode Operation (RCR[7]): Default = Disabled ........................124

Absolute Maximum Ratings . . . . . . . . . . . . . . . . 125

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 126

Table 26. Electrical Characteristics and Operating Conditions . 126

Table 27. Temperature Compensated Refresh Specifications and

Conditions ....................................................................... 127

Table 28. Partial Array Refresh Specifications and Conditions . 127

Table 29. Deep Power-Down Specifications .......................... 127

Functional Description . . . . . . . . . . . . . . . . . . . . 107

Power-Up Initialization .................................................................................... 107

Figure 22. Power-Up Initialization Timing............................. 108

Bus Operating Modes . . . . . . . . . . . . . . . . . . . . . 108

Asynchronous Mode ........................................................................................108

Figure 23. READ Operation (ADV# LOW)............................. 108

Figure 24. WRITE Operation (ADV# LOW) ........................... 109

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 128

Figure 37. AC Input/Output Reference Waveform................. 128

Figure 38. Output Load Circuit ........................................... 128

Table 30. Output Load Circuit ............................................ 128

Table 31. Asynchronous READ Cycle Timing Requirements .... 129

Table 32. Burst READ Cycle Timing Requirements ................ 130

Table 33. Asynchronous WRITE Cycle Timing Requirements ... 131

Table 34. Burst WRITE Cycle Timing Requirements ............... 131

Page Mode READ Operation ........................................................................109

Figure 25. Page Mode READ Operation (ADV# LOW)............. 110

Burst Mode Operation .....................................................................................110

Figure 26. Burst Mode READ (4-word burst) ........................ 111

Figure 27. Burst Mode WRITE (4-word burst)....................... 111

Timing Diagrams ................................................................................................ 132

Figure 39. Initialization Period ........................................... 132

Table 35. Initialization Timing Parameters ........................... 132

Figure 40. Asynchronous READ.......................................... 133

Table 36. Asynchronous READ Timing Parameters ................ 133

Figure 41. Asynchronous READ Using ADV# ........................ 135

Table 37. Asynchronous READ Timing Parameters Using ADV# 135

Figure 42. Page Mode READ .............................................. 137

Table 38. Asynchronous READ Timing Parameters—Page Mode

Operation ....................................................................... 137

Figure 43. Single-Access Burst READ Operation—Variable

Latency .......................................................................... 139

Table 39. Burst READ Timing Parameters—Single Access, Variable

Latency .......................................................................... 139

Figure 44. Four-word Burst READ Operation—Variable Latency 141

Table 40. Burst READ Timing Parameters—4-word Burst ....... 142

Figure 45. Four-word Burst READ Operation (with LB#/UB#). 143

Table 41. Burst READ Timing Parameters—4-word Burst with LB#/

UB# ............................................................................... 144

Figure 46. READ Burst Suspend ......................................... 145

Table 42. Burst READ Timing Parameters—Burst Suspend ..... 145

Figure 47. Continuous Burst READ Showing an Output Delay with

BCR[8] = 0 for End-of-Row Condition ................................. 146

Table 43. Burst READ Timing Parameters—BCR[8] = 0 ......... 146

Figure 48. CE#-Controlled Asynchronous WRITE .................. 147

Mixed-Mode Operation ................................................................................... 112

WAIT Operation ............................................................................................... 112

Figure 28. Wired or WAIT Configuration .............................. 112

LB#/UB# Operation .......................................................................................... 113

Figure 29. Refresh Collision During READ Operation.............. 113

Figure 30. Refresh Collision During WRITE Operation ............ 114

Low-Power Operation . . . . . . . . . . . . . . . . . . . . . 114

Standby Mode Operation ................................................................................ 114

Temperature Compensated Refresh ........................................................... 114

Partial Array Refresh ........................................................................................ 115

Deep Power-Down Operation ...................................................................... 115

Configuration Registers . . . . . . . . . . . . . . . . . . . . 115

Access Using CRE .............................................................................................. 115

Figure 31. Configuration Register WRITE, Asynchronous Mode Fol-

lowed by READ ................................................................ 116

Figure 32. Configuration Register WRITE, Synchronous Mode Fol-

lowed by READ0............................................................... 117

Bus Configuration Register ............................................................................. 117

Table 18. Bus Configuration Register Definition ....................118

Table 19. Sequence and Burst Length .................................119

Burst Length (BCR[2:0]): Default = Continuous Burst ...................... 119

Burst Wrap (BCR[3]): Default = No Wrap .......................................... 119

S71GS256/128N_00_A0 December 17, 2004

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