DA14581
Bluetooth Low Energy 4.2 SoC with Optimized Boot Time
General Description
FINAL
AES-128 bit encryption Processor
Memories
The DA14581 integrated circuit is an optimized version
32 kB One-Time-Programmable (OTP) memory
of the DA14580, offering a reduced boot time and sup-
42 kB System SRAM
porting up to 8 connections. It has a fully integrated
84 kB ROM
radio transceiver and baseband processor for
Blue-
8 kB Retention SRAM
tooth
®
low energy.
It can be used as a standalone
Power management
application processor or as a data pump in hosted sys-
Integrated Buck/Boost DC-DC converter
tems.
P0, P1 and P2 ports with 3.3 V tolerance
Easy decoupling of only 4 supply pins
The DA14581 supports a flexible memory architecture
Supports coin (typ. 3.0 V) and alkaline (typ. 1.5 V)
for storing Bluetooth profiles and custom application
battery cells
code, which can be updated over the air (OTA). The
10-bit ADC for battery voltage measurement
qualified
Bluetooth low energy
protocol stack and the
Digital controlled oscillators
HCI ready software are stored in a dedicated ROM. All
16 MHz crystal (±20 ppm max) and RC oscillator
software runs on the ARM
®
Cortex
®
-M0 processor via
32 kHz crystal (±50 ppm, ±500 ppm max) and
a simple scheduler.
RCX oscillator
The
Bluetooth low energy
firmware includes the
General purpose, Capture and Sleep timers
L2CAP service layer protocols, Security Manager
Digital interfaces
(SM), Attribute Protocol (ATT), the Generic Attribute
Gen. purpose I/Os: 14 (WLCSP34), 24 (QFN40)
Profile (GATT) and the Generic Access Profile (GAP).
2 UARTs with hardware flow control up to 1 MBd
All profiles published by the Bluetooth SIG as well as
SPI+™ interface
custom profiles are supported.
I2C bus at 100 kHz, 400 kHz
3-axes capable Quadrature Decoder
The transceiver interfaces directly to the antenna and
Analog interfaces
is fully compliant with the
Bluetooth 4.2
standard.
4-channel 10-bit ADC
The DA14581 has dedicated hardware for the Link
Radio transceiver
Layer implementation of
Bluetooth low energy
and
Fully integrated 2.4 GHz CMOS transceiver
interface controllers for enhanced connectivity capabili-
Single wire antenna: no RF matching or RX/TX
ties.
switching required
Supply current at VBAT3V:
Features
TX: 3.4 mA, RX: 3.7 mA (with ideal DC-DC)
Complies with
Bluetooth V4.2,
ETSI EN 300 328 and
0 dBm transmit output power
-20 dBm output power in “Near Field Mode”
EN 300 440 Class 2 (Europe), FCC CFR47 Part 15
-93 dBm receiver sensitivity
(US) and ARIB STD-T66 (Japan)
Supports up to 8 Bluetooth low energy connections
Packages:
Fast cold boot in less than 30 ms
Ultra-Thin WLCSP 34 pins, 2.436 mm x 2.436 mm
Processing power
x 0.334 mm
16 MHz 32 bit ARM Cortex-M0 with SWD inter-
WLCSP 34 pins, 2.436 mm x 2.436 mm
face
x 0.511 mm
Dedicated Link Layer Processor
QFN 40 pins, 5 mm x 5 mm
________________________________________________________________________________________________
System Diagram
Datasheet
CFR0011-120-01
Revision 3.2
1 of 233
17-Jan-2017
© 2014 Dialog Semiconductor
DA14581
Bluetooth Low Energy 4.2 SoC with Optimized Boot Time
Contents
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
System Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
13 I2C Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 8
4 System Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.1 INTERNAL BLOCKS . . . . . . . . . . . . . . . . . . . . . 9
4.2 FUNCTIONAL MODES . . . . . . . . . . . . . . . . . . . 9
4.3 OTP MEMORY LAYOUT . . . . . . . . . . . . . . . . 10
4.3.1 OTP Header. . . . . . . . . . . . . . . . . . . . . . 10
4.4 SYSTEM START PROCEDURE . . . . . . . . . . . .11
4.4.1 Power/Wake-Up Sequence . . . . . . . . . . 12
4.4.2 OTP Mirroring . . . . . . . . . . . . . . . . . . . . 13
4.4.3 BootROM Sequence . . . . . . . . . . . . . . . 14
4.5 POWER SUPPLY CONFIGURATION . . . . . . 16
4.5.1 Power Domains . . . . . . . . . . . . . . . . . . . 16
4.5.2 Power Modes . . . . . . . . . . . . . . . . . . . . . 17
4.5.3 Retention Registers . . . . . . . . . . . . . . . . 17
5 Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.1 POR, HW AND SW RESET . . . . . . . . . . . . . . 19
6 ARM Cortex-M0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.1 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.2 SYSTEM TIMER (SYSTICK). . . . . . . . . . . . . . 22
6.3 WAKE-UP INTERRUPT CONTROLLER. . . . . 22
6.4 REFERENCE . . . . . . . . . . . . . . . . . . . . . . . . . 22
7 AMBA Bus Overview. . . . . . . . . . . . . . . . . . . . . . . . 23
8 Patch Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
9 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
10 Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . 27
10.1 ARBITRATION . . . . . . . . . . . . . . . . . . . . . . . 27
11 Clock Generation. . . . . . . . . . . . . . . . . . . . . . . . . . 28
11.1 CRYSTAL OSCILLATORS . . . . . . . . . . . . . . 28
11.1.1 FRequency Control (16 MHz Crystal) . 28
11.1.2 Automated Trimming Mechanism . . . . 28
11.2 RC OSCILLATORS . . . . . . . . . . . . . . . . . . . . 29
11.2.1 Frequency Calibration . . . . . . . . . . . . . 29
11.3 SYSTEM CLOCK GENERATION . . . . . . . . . 30
13.1 I2C BUS TERMS . . . . . . . . . . . . . . . . . . . . . . 33
13.1.1 Bus Transfer Terms . . . . . . . . . . . . . . . 34
13.2 I2C BEHAVIOR . . . . . . . . . . . . . . . . . . . . . . . 34
13.2.1 START and STOP Generation . . . . . . . 35
13.2.2 Combined Formats . . . . . . . . . . . . . . . 35
13.3 I2C PROTOCOLS . . . . . . . . . . . . . . . . . . . . . 35
13.3.1 START and STOP Conditions . . . . . . . 35
13.3.2 Addressing Slave Protocol. . . . . . . . . . 35
13.3.3 Transmitting and Receiving Protocols . 36
13.4 MULTIPLE MASTER ARBITRATION . . . . . . 38
13.5 CLOCK SYNCHRONIZATION . . . . . . . . . . . 39
13.6 OPERATION MODES . . . . . . . . . . . . . . . . . . 40
13.6.1 Slave Mode Operation . . . . . . . . . . . . . 40
13.6.2 Master Mode Operation . . . . . . . . . . . . 42
13.6.3 Disabling the I2C Controller . . . . . . . . . 42
14 UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
14.1 UART (RS232) SERIAL PROTOCOL . . . . . . 44
14.2 IRDA 1.0 SIR PROTOCOL . . . . . . . . . . . . . . 44
14.3 CLOCK SUPPORT . . . . . . . . . . . . . . . . . . . . 45
14.4 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . 46
14.5 PROGRAMMABLE THRE INTERRUPT . . . . 46
14.6 SHADOW REGISTERS . . . . . . . . . . . . . . . . 48
14.7 DIRECT TEST MODE . . . . . . . . . . . . . . . . . . 48
15 SPI+ Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
15.1 OPERATION WITHOUT FIFOS . . . . . . . . . . 49
15.2 9 BITS MODE . . . . . . . . . . . . . . . . . . . . . . . . 50
16 Quadrature Decoder . . . . . . . . . . . . . . . . . . . . . . . 53
17 Wake-Up Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
18 General Purpose Timers. . . . . . . . . . . . . . . . . . . . 55
18.1 TIMER 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
18.2 TIMER 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
19 Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . 59
20 Keyboard Controller . . . . . . . . . . . . . . . . . . . . . . . 60
20.1 KEYBOARD SCANNER . . . . . . . . . . . . . . . . 60
20.2 GPIO INTERRUPT GENERATOR . . . . . . . . 60
11.4 GENERAL CLOCK CONSTRAINTS . . . . . . . 31
12 OTP Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
12.1 OPERATING MODES . . . . . . . . . . . . . . . . . . 32
12.2 AHB MASTER INTERFACE . . . . . . . . . . . . . 32
FINAL
Datasheet
CFR0011-120-01
Revision 3.2
2 of 233
17-Jan-2017
© 2014 Dialog Semiconductor
DA14581
Bluetooth Low Energy 4.2 SoC with Optimized Boot Time
21 Input/Output Ports. . . . . . . . . . . . . . . . . . . . . . . . . 62
21.1 PROGRAMMABLE PIN ASSIGNMENT . . . . 62
21.2 GENERAL PURPOSE PORT REGISTERS . 62
21.2.1 Port Data Register . . . . . . . . . . . . . . . . 63
21.2.2 Port Set Data Output Register . . . . . . . 63
21.2.3 Port Reset Data Output Register . . . . . 63
21.3 FIXED ASSIGNMENT FUNCTIONALITY . . . 63
22 General Purpose ADC. . . . . . . . . . . . . . . . . . . . . . 64
22.1 INPUT CHANNELS AND INPUT SCALE . . . 64
22.2 STARTING THE ADC AND SAMPLING RATE
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
22.3 NON-IDEAL EFFECTS . . . . . . . . . . . . . . . . . 65
22.4 CHOPPING . . . . . . . . . . . . . . . . . . . . . . . . . . 65
22.5 OFFSET CALIBRATION . . . . . . . . . . . . . . . . 65
22.6 ZERO-SCALE ADJUSTMENT . . . . . . . . . . . 66
22.7 COMMON MODE ADJUSTMENT. . . . . . . . . 66
22.8 INPUT IMPEDANCE, INDUCTANCE AND IN-
PUT SETTLING. . . . . . . . . . . . . . . . . . . . . . . . 66
22.9 DELAY COUNTER . . . . . . . . . . . . . . . . . . . . 67
23 Power Management. . . . . . . . . . . . . . . . . . . . . . . . 68
24 BLE Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
24.1 EXCHANGE MEMORY . . . . . . . . . . . . . . . . . 71
24.2 PROGRAMMING BLE WAKE UP IRQ . . . . . 73
24.3 SWITCH FROM ACTIVE MODE TO DEEP
SLEEP MODE . . . . . . . . . . . . . . . . . . . . . . . . . 73
24.4 SWITCH FROM DEEP SLEEP MODE TO AC-
TIVE MODE. . . . . . . . . . . . . . . . . . . . . . . . . . . 74
24.4.1 Switching at Anchor Points . . . . . . . . . 74
24.4.2 Switching Due to an External Event . . 76
25 Radio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
25.1 RECEIVER . . . . . . . . . . . . . . . . . . . . . . . . . . 77
25.2 SYNTHESIZER . . . . . . . . . . . . . . . . . . . . . . . 77
25.3 TRANSMITTER . . . . . . . . . . . . . . . . . . . . . . . 77
25.4 RFIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
25.5 BIASING . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
25.6 CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
26 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
27 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
28 Package Information . . . . . . . . . . . . . . . . . . . . . . 229
28.1 MOISTURE SENSITIVITY LEVEL (MSL) . . 229
28.2 WLCSP HANDLING . . . . . . . . . . . . . . . . . . 229
28.3 SOLDERING INFORMATION . . . . . . . . . . . 229
28.4 PACKAGE OUTLINES . . . . . . . . . . . . . . . . 230
FINAL
Datasheet
CFR0011-120-01
Revision 3.2
3 of 233
17-Jan-2017
© 2014 Dialog Semiconductor
DA14581
Bluetooth Low Energy 4.2 SoC with Optimized Boot Time
1
Block Diagram
FINAL
24 April 2012
ARM Cortex M0
XTAL
32.768 kHz
XTAL
16 MHz
DCDC
(BUCK/BOOST)
LDO
SYS
LDO
RET
LDO
LDO
LDO
SYS
SYS
RF
RC
16 MHz
RC
32 kHz
RCX
CORE
BLE Core
POReset
SWD (JTAG)
System/
Exchange
RAM
42 kB
AES-128
LINK LAYER
HARDWARE
Radio
Transceiver
Memory Controller
Ret. RAM2
3 kB
Ret. RAM3
2 kB
Ret. RAM4
1 kB
APB bridge
Ret. RAM
2 kB
POWER/CLOCK
Management (PMU)
KEYBOARD
CTRL
OTP
32 kB
ROM
84 kB
DMA
OTPC
FIFO
FIFO
Timer 2
3xPWM
GPIO MULTIPLEXING
Figure 1: DA14581 Block Diagram
Datasheet
CFR0011-120-01
Revision 3.2
4 of 233
FIFO
Timer 0
1xPWM
© 2014 Dialog Semiconductor
QUAD
DECODER
WAKE UP
TIMER
SW TIMER
GP ADC
UART2
UART
SPI
I2C
17-Jan-2017
DA14581
Bluetooth Low Energy 4.2 SoC with Optimized Boot Time
2
Pinout
The DA14581 comes in three packages:
• A Wafer Level Chip Scale Package (WLCSP) with
34 balls (normal thickness and ultra-thin)
FINAL
• A Quad Flat Package No Leads (QFN) with 40 pins
The actual pin/ball assignment is depicted in the follow-
ing figures:
1
A
B
C
D
E
F
2
3
m
FI
O
4
R
FI
O
p
5
N
D
G
6
VP
P
XT
XT
AL
AL
16
16
M
M
m
p
VD
C
P1
D
C
_3
_R
F
R
P0
_1
2
LK
G
2
G
N
D
_C
P0
_
D
IO
SW
P1
_
G
N
D
D
P1
_1
P0
_4
SW
G
VB
AT
_R
F
VB
AT
1V
P1
_0
DA14581 (Top View)
Figure 2: WLCSP Ball Assignment
40
39
38
37
36
35
34
33
32
P0_0
P0_1
P0_2
P0_3
NC
P0_4
P0_5
P2_1
P0_6
P0_7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
31
30
29
28
27
VDCDC_RF
RFIOm
RFIOp
P2_9
P2_8
P2_6
P2_0
P2_7
P2_5
VPP
XT
AL
32
Kp
XT
AL
32
Km
H
C
VB
AT
3V
IT
C
D
VD
C
SW
G
N
D
P0
_7
P0
_6
R
ST
P0
_
N
5
P0
_
3
P0
_0
N
D
XTAL16Mm
XTAL16Mp
P1_3
P1_2
SW_CLK
SWDIO
P1_1
VBAT1V
P1_0
SWITCH
DA14581
(Top View)
26
25
24
23
22
21
VBAT_RF
VBAT3V
P2_2
XTAL32Km
XTAL32Kp
P2_3
Pin 0: GND
plane
Figure 3: QFN40 Pin Assignment
Datasheet
CFR0011-120-01
Revision 3.2
5 of 233
VDCDC
P2_4
GND
RST
17-Jan-2017
© 2014 Dialog Semiconductor
ARM Technology
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