Power Supply has internal 25A/250V fast blow fuse on the DC input negative line
1.74 lbs (0.789 kg)
D1U54-D-450-12- Hx4C
P-Q Curve (Airflow F to B)
11.0
10.0
9.0
8.0
Airflow (CFM)
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0.0
0
100
200
300
400
500
600
700
800
-900
-800
-700
P-Q Curve (Airflow B to F)
13.0
12.0
11.0
10.0
9.0
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0.0
-600
-500
-400
-300
-200
-100
0
Airflow (CFM)
8.0
Back Pressure (Pa)
Back Pressure (Pa)
Notes:
1. The above curves represent provisional performance based upon a similar product using a 20mm thickness fan; these curves will be updated on later revisions of this datasheet.
2. Curves recorded at room ambient (circa 25°C).
3. Curves generated with intermal fan running at 100% duty cycle while variying back pressure.
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D1U54-D-450-12-HXXC.A05
Page 2 of 9
PROTECTION CHARACTERISTICS
Output
Parameter
Overtemperature (intake)
Overvoltage
12V
Conditions
54mm 1U Front End DC-DC Power Supply Converter
Min.
13.5
Typ.
75
14.5
Max.
Autorestart with 4°C hysteresis for recovery (warning issued at 70°C)
Latching
The output shall shutdown when an overcurrent condition is detected.
It will auto restart after 1sec; however if the overcurrent condition is redetected the output will
once again shutdown. The output will once again re-start, however if the overcurrent condition
persists it will latch of after the fifth unsuccessful attempt.
To reset the latch it will be necessary to toggle the PS_ON_L signal or recycle the incoming
DC source.
Latching
The output shall shutdown when an overcurrent is detected.
It will auto restart after 2sec; however if the overcurrent is re-detected the output will once
again shutdown.
This cycle will occur indefinitely while the overcurrent condition persists.
D1U54-D-450-12-HxxC Series
Units
°C
Vdc
Overcurrent (target)
42
47
Adc
Overvoltage
5VSB
Overcurrent
5.4
2.2
6.0
3.5
Vdc
Adc
ISOLATION CHARACTERISTICS
Parameter
Insulation Safety Rating/Test Voltage
Isolation
EMISSIONS AND IMMUNITY
Conditions
Input to Output - Reinforced
Output to Chassis
Min.
1000
500
Typ.
Max.
Units
Vdc
Vdc
Characteristic
Input Current Harmonics
Voltage Fluctuation and Flicker
Conducted Emissions
ESD Immunity
Radiated Field Immunity
Electrical Fast Transients/Burst Immunity
Surge Immunity
RF Conducted Immunity
Magnetic Field Immunity
Voltage Dips and Interruptions – Target (TBC)
STATUS INDICATORS AND CONTROL SIGNALS
INPUT LED
Condition
Input Voltage Present
Input Voltage fault or warning
Input off
POWER LED
Condition
Standard
IEC/EN 61000-3-2
IEC/EN 61000-3-3
FCC 47 CFR Part 15
CISPR 22/EN55022
IEC/EN 61000-4-2
IEC/EN 61000-4-3
IEC/EN 61000-4-4
IEC/EN 61000-4-5
IEC/EN 61000-4-6
IEC/EN 61000-4-8
-----
Compliance
Complies
Complies
Class A with 6dB margin
Level 4 criteria A
Level 3 criteria B
Level 3 criteria A
Level 3, Criteria A (normal performance), common mode 2kV 12ohm, differential mode
The signal output is driven high when input source is available and within acceptable limits. The
output is driven low to indicate loss of input power.
There is a minimum of 1ms pre-warning time before the signal is driven low prior to the PWR_OK
signal going low. The power supply must ensure that this interface signal provides accurate status
when DC input power is lost.
INPUT_OK (DC Source) Output
PW_OK (Output OK)
Output
SMB_ALERT
(FAULT/WARNING)
Output
PRESENT_L
Output
(Power Supply Absent)
PS_ON
Input
(Power Supply
Enable/Disable
PS_KILL
Input
ADDR (Address Select) Input
Pulled up internally via 10K to V
DD
*.
A logic high >2.0Vdc
A logic low <0.8Vdc
Driven low by internal CMOS buffer
(open drain output).
The signal is asserted, driven high, by the power supply to indicate that all outputs are valid. If any of Pulled up internally via 10K to V
DD
*.
the outputs fail then this output will be hi-Z or driven low.
A logic high >2.0Vdc
The output is driven low to indicate that the Main output is outside of lower limit of regulation.
A logic low <0.8Vdc
Driven low by internal CMOS buffer
(open drain output).
The signal output is driven low to indicate that the power supply has detected a warning or fault and Pulled up internally via 10K to V
DD
*.
is intended to alert the system. This output must be driven high when the power is operating
A logic high >2.0Vdc
correctly (within specified limits).
A logic low <0.8Vdc
The signal will revert to a high level when the warning/fault stimulus (that caused the alert) is
Driven low by internal CMOS buffer
removed.
(open drain output).
The signal is used to detect the presence (installation) of a PSU by the host system. The signal is
Passive connection to +VSB_Return.
connected to PSU logic +VSB_Return within the power module.
A logic low <0.8Vdc
This signal is pulled up internally to the internal housekeeping supply (within the power supply). The Pulled up internally via 10K to V
DD
*.
power supply main 12Vdc output will be enabled when this signal is pulled low to +VSB_Return.
A logic high >2.0Vdc
In the low state the signal input shall not source more than 1mA of current. The 12Vdc output will be A logic low <0.8Vdc
disabled when the input is driven higher than 2.4V, or open circuited. Cycling this signal shall clear
Input is via CMOS Schmitt trigger
latched fault conditions.
buffer.
This signal is used during hot swap to disable the main output during hot swap extraction. The input is Pulled up internally via 10K to V
DD
*.
pulled up internally to V
DD
* (within the power supply).
A logic high >2.0Vdc
The signal is provided on a short (lagging pin) and should be connected to +VSB_Return.
A logic low <0.8Vdc
Input is via CMOS Schmitt trigger
buffer.
An analog input that is used to set the address of the internal slave devices (EEPROM and
DC voltage between the limits of 0 and
microprocessor) used for digital communications.
+3.3Vdc.
Connection of a suitable resistor to +VSB_Return, in conjunction with an internal resistor divider
chain, will configure the required address (see ADDR Address Selection:
#ADDRSelect)
A serial clock line compatible with PMBus
TM
Power Systems Management Protocol Part 1 – General
Requirements Rev 1.1.
No additional internal capacitance is added that would affect the speed of the bus.
The signal is provided with a series isolator device to disconnect the internal power supply bus in the
event that the power module is unpowered,
A serial data line compatible with PMBus
TM
Power Systems Management Protocol Part 1 – General
Requirements Rev 1.1.
The signal is provided with a series isolator device to disconnect the internal power supply bus in the
event that the power module is unpowered,
Remote sense connections intended to be connected at and sense the voltage at the point of load.
The voltage sense will interact with the internal module regulation loop to compensate for voltage
drops due to connection resistance between the output connector and the load.
If remote sense compensation is not required then the voltage can be configured for local sense
by:
1.
V1_SENSE directly connected to power gold fingers P9-P16 (inclusive)
2.
V1_SENSE_RTN directly connected to gold fingers P1 to P8 (inclusive)
The current sharing signal is connected between sharing units (forming an ISHARE bus). It is an
input and/or an output (bi-directional analog bus) as the voltage on the line controls the current
share between sharing units.
A power supply will respond to a change in this voltage but a power supply can also change the
voltage depending on the load drawn from it.
On a single unit the voltage on the pin (and the common ISHARE bus would read 8VDC at 100%
load (module capability). For two identical units sharing the same 100% load this would read
4VDC for perfect current sharing (i.e. 50% module load capability per unit).
V
IL
is 0.8V maximum
V
OL
is 0.4V maximum when sinking
3mA
V
IH
is 2.1V minimum
V
IL
is 0.8V maximum
V
OL
is 0.4V maximum when sinking
3mA
V
IH
is 2.1V minimum
Compensation for a up to 0.12Vdc
total connection drop (output and
return connections).
SCL (Serial Clock)
Both
SDA (Serial Data)
Both
V1_SENSE
V1SENSE_RTN
Input
ISHARE
Bi-
Directional
Digital Bus
Analogue voltage:
+8V maximum; 10K to +12V_RTN
*VDD is an internal voltage rail derived from VSB and an internal housekeeping rail (“diode ORed”) and is compatible with the voltage tolerances of VSB).
www.murata-ps.com/support
D1U54-D-450-12-HXXC.A05
Page 4 of 9
54mm 1U Front End DC-DC Power Supply Converter
TIMING SPECIFICATIONS
Turn-On Delay & Output Rise Time:
Power-on-delay, Risetime, and signaling
V1 PS_ON delay
D1U54-D-450-12-HxxC Series
DC input
DC input
Vsb
Vsb Risetime
Vsb Power-on-delay
V1
V1 Risetime
V1 Power-on-delay
PS_ON
Vsb
V1
V1 PS_ON delay
PS_ON
DC_OK delay
DC_input OK
PWOK delay
PWOK
PWOK
DC_input OK
1.
2.
The turn-on delay after application of DC input within the operating range shall as defined in the following tables.
The output rise times shall be measured from 10% of the nominal output to the lower limit of the regulation band as defined in the following tables.
Time
Vsb Rise time
V1 Rise time
Vsb Power-on-delay
V1 Power-on-delay
V1 PS_ON delay
V1 PWOK delay
DCOK (Input) detect
TIMING SPECIFICATIONS
Turn-Off (Shutdown by PS_ON)
Min
2ms
10ms
300ms
400ms
100ms
300ms
270ms
Max
170ms
220ms
1600ms
2000ms
300ms
450ms
1000ms
Turn off fall time and signaling
DC input
Turn-Off Timing
V1 Fall time
V1 PS_OFF delay
PW_OK delay off
Min
-
0ms
1.2ms
Max
-
6.0ms
Notes
Must be monotonic
Vsb
V1
V1 PS_OFF delay
PS_ON
V1 Falltime
DC Input_OK
PW_OK delayoff
PWOK
1. Note this characteristic is applicable for the main 12Vdc output shutdown from PS_ON pulled high.
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