N93C66
4 Kb Microwire Serial CMOS
EEPROM
Description
The N93C66 is a 4 kb CMOS Serial EEPROM device which is
organized as either 256 registers of 16 bits (ORG pin at V
CC
) or 512
registers of 8 bits (ORG pin at GND). Each register can be written (or
read) serially by using the DI (or DO) pin. The device features
sequential read and self−timed internal write with auto−clear. On−chip
Power−On Reset circuitry protects the internal logic against powering
up in the wrong state.
Features
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High Speed Operation: 4 MHz
1.7 V to 5.5 V Supply Voltage Range
Selectable x8 or x16 Memory Organization
Sequential Read
Software Write Protection
Power−up Inadvertent Write Protection
Low Power CMOS Technology
1,000,000 Program/Erase Cycles
100 Year Data Retention
Industrial Temperature Range
8−pad TDFN Package
These Devices are Pb−Free, Halogen Free/BFR Free, and RoHS
Compliant
V
CC
TDFN−8
VP2 SUFFIX
CASE 511AK
PIN CONFIGURATION
(Top View)
CS
SK
DI
DO
2
3
4
1
8 V
CC
7 NC
6 ORG
5 GND
TDFN (VP2)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
ORG
CS
N93C66
SK
DI
DO
GND
Figure 1. Functional Symbol
N93C66 Selectable Organization:
When the ORG pin is connected to V
CC
, the x16 organization is
selected. When it is connected to ground, the x8 organization is
selected. If the ORG pin is left unconnected, then an internal pull−up
device will select the x16 organization.
©
Semiconductor Components Industries, LLC, 2017
1
October, 2017 − Rev. 0
Publication Order Number:
N93C66/D
N93C66
Table 1. PIN FUNCTION
Pin Name
CS
SK
DI
DO
Function
Chip Select
Clock Input
Serial Data Input
Serial Data Output
Pin Name
V
CC
GND
ORG
NC
Function
Power Supply
Ground
Memory Organization
No Connection
Table 2. ABSOLUTE MAXIMUM RATINGS
Parameters
Storage Temperature
Voltage on Any Pin with Respect to Ground (Note 1)
Ratings
−65 to +150
−0.5 to +6.5
Units
°C
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. The DC input voltage on any pin should not be lower than −0.5 V or higher than V
CC
+ 0.5 V. During transitions, the voltage on any pin may
undershoot to no less than −1.5 V or overshoot to no more than V
CC
+ 1.5 V, for periods of less than 20 ns.
Table 3. RELIABILITY CHARACTERISTICS
(Note 2)
Symbol
N
END
(Note 3)
T
DR
Endurance
Data Retention
Parameter
Min
1,000,000
100
Units
Program / Erase Cycles
Years
2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
3. Block Mode, V
CC
= 5 V, 25°C.
Table 4. D.C. OPERATING CHARACTERISTICS
(
V
CC
= +1.7 V to +5.5 V, T
A
= −40°C to +85°C unless otherwise specified.)
Symbol
I
CC1
I
CC2
I
SB1
I
SB2
I
LI
I
LO
V
IL1
V
IH1
V
IL2
V
IH2
V
OL1
V
OH1
V
OL2
V
OH2
Parameter
Power Supply Current
(Write)
Power Supply Current
(Read)
Power Supply Current
(Standby) (x8 Mode)
Power Supply Current
(Standby) (x16 Mode)
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
f
SK
= 2 MHz
V
IN
= GND or V
CC
,
CS = GND ORG = GND
V
IN
= GND or V
CC
, CS = GND
ORG = Float or V
CC
V
IN
= GND to V
CC
V
OUT
= GND to V
CC
,
CS = GND
4.5 V
≤
V
CC
< 5.5 V
4.5 V
≤
V
CC
< 5.5 V
1.7 V
≤
V
CC
< 4.5 V
1.7 V
≤
V
CC
< 4.5 V
4.5 V
≤
V
CC
< 5.5 V, I
OL
= 3.0 mA
4.5 V
≤
V
CC
< 5.5 V, I
OH
= −400
mA
1.7 V
≤
V
CC
< 4.5 V, I
OL
= 1 mA
1.7 V
≤
V
CC
< 4.5 V, I
OH
= −100
mA
V
CC
− 0.2
2.4
0.2
T
A
= −40°C to +85°C
T
A
= −40°C to +85°C
T
A
= −40°C to +85°C
T
A
= −40°C to +85°C
−0.1
2
0
V
CC
x 0.7
Test Conditions
Min
Max
1
500
2
1
1
1
0.8
V
CC
+ 1
V
CC
x 0.2
V
CC
+ 1
0.4
Units
mA
mA
mA
mA
mA
mA
V
V
V
V
V
V
V
V
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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N93C66
Table 5. PIN CAPACITANCE
(T
A
= 25°C, f = 1.0 MHz, V
CC
= +5.0 V)
Symbol
C
OUT
(Note 4)
C
IN
(Note 4)
Test
Output Capacitance (DO)
Input Capacitance (CS, SK, DI, ORG)
Conditions
V
OUT
= 0 V
V
IN
= 0 V
Min
Typ
Max
5
5
Units
pF
pF
4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
Table 6. A.C. CHARACTERISTICS
(V
CC
= +1.7 V to +5.5 V, T
A
= −40°C to +85°C, unless otherwise specified.) (Note 5)
V
CC
< 4.5 V
Symbol
t
CSS
t
CSH
t
DIS
t
DIH
t
PD1
t
PD0
t
HZ
(Note 6)
t
EW
t
CSMIN
t
SKHI
t
SKLOW
t
SV
SK
MAX
CS Setup Time
CS Hold Time
DI Setup Time
DI Hold Time
Output Delay to 1
Output Delay to 0
Output Delay to High−Z
Program/Erase Pulse Width
Minimum CS Low Time
Minimum SK High Time
Minimum SK Low Time
Output Delay to Status Valid
Maximum Clock Frequency
DC
0.25
0.25
0.25
0.25
2000
DC
Parameter
Min
50
0
100
100
0.25
0.25
100
4
0.1
0.1
0.1
0.1
4000
Max
V
CC
.
4.5 V
Min
50
0
50
50
0.1
0.1
100
4
Max
Units
ns
ns
ns
ns
ms
ms
ns
ms
ms
ms
ms
ms
kHz
5. Test conditions according to “A.C. Test Conditions” table.
6. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate
AEC−Q100 and JEDEC test methods.
Table 7. POWER−UP TIMING
(Notes 7, 8)
Symbol
t
PUR
t
PUW
Power−up to Read Operation
Power−up to Write Operation
Parameter
Max
1
1
Units
ms
ms
7. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate
AEC−Q100 and JEDEC test methods.
8. t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated.
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N93C66
Table 8. A.C. TEST CONDITIONS
Input Rise and Fall Times
Input Pulse Voltages
Timing Reference Voltages
Input Pulse Voltages
Timing Reference Voltages
Output Load
≤
50 ns
0.4 V to 2.4 V
0.8 V, 2.0 V
0.2 V
CC
to 0.7 V
CC
0.5 V
CC
4.5 V
≤
V
CC
≤
5.5 V
4.5 V
≤
V
CC
≤
5.5 V
1.7 V
≤
V
CC
≤
4.5 V
1.7 V
≤
V
CC
≤
4.5 V
Current Source I
OLmax
/I
OHmax
; CL = 100 pF
Device Operation
The N93C66 is a 4096−bit nonvolatile memory intended
for use with industry standard microprocessors. The
N93C66 can be organized as either registers of 16 bits or 8
bits. When organized as X16, seven 11−bit instructions
control the reading, writing and erase operations of the
device. When organized as X8, seven 12−bit instructions
control the reading, writing and erase operations of the
device. The device operates on a single power supply and
will generate on chip, the high voltage required during any
write operation.
Instructions, addresses, and write data are clocked into the
DI pin on the rising edge of the clock (SK). The DO pin is
normally in a high impedance state except when reading data
from the device, or when checking the ready/busy status
after a write operation. The serial communication protocol
follows the timing shown in Figure 2.
Table 9. INSTRUCTION SET
Address
Instruction
READ
ERASE
WRITE
EWEN
EWDS
ERAL
WRAL
Start Bit
1
1
1
1
1
1
1
Opcode
10
11
01
00
00
00
00
x8
A8−A0
A8−A0
A8−A0
11XXXXXXX
00XXXXXXX
10XXXXXXX
01XXXXXXX
The ready/busy status can be determined after the start of
internal write cycle by selecting the device (CS high) and
polling the DO pin; DO low indicates that the write
operation is not completed, while DO high indicates that the
device is ready for the next instruction. If necessary, the DO
pin may be placed back into a high impedance state during
chip select by shifting a dummy “1” into the DI pin. The DO
pin will enter the high impedance state on the rising edge of
the clock (SK). Placing the DO pin into the high impedance
state is recommended in applications where the DI pin and
the DO pin are to be tied together to form a common DI/O
pin.
The format for all instructions sent to the device is a
logical “1” start bit, a 2−bit (or 4−bit) opcode, 8−bit address
(an additional bit when organized X8) and for write
operations a 16−bit data field (8−bit for X8 organizations).
The instruction format is shown in Instruction Set table.
Data
x16
A7−A0
A7−A0
A7−A0
D7−D0
D15−D0
x8
x16
Comments
Read Address AN – A0
Clear Address AN – A0
Write Address AN – A0
Write Enable
Write Disable
Clear All Addresses
D7−D0
D15−D0
Write All Addresses
11XXXXXX
00XXXXXX
10XXXXXX
01XXXXXX
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N93C66
Read
Upon receiving a READ command and an address
(clocked into the DI pin), the DO pin of the N93C66 will
come out of the high impedance state and, after sending an
initial dummy zero bit, will begin shifting out the data
addressed (MSB first). The output data bits will toggle on
the rising edge of the SK clock and are stable after the
specified time delay (t
PD0
or t
PD1
).
For the N93C66 after the initial data word has been shifted
out and CS remains asserted with the SK clock continuing
to toggle, the device will automatically increment to the next
address and shift out the next data word in a sequential
READ mode. As long as CS is continuously asserted and SK
continues to toggle, the device will keep incrementing to the
next address automatically until it reaches to the end of the
address space, then loops back to address 0. In the sequential
READ mode, only the initial data word is preceeded by a
t
SKHI
SK
t
DIS
DI
t
CSS
CS
t
DIS
DO
VALID
dummy zero bit. All subsequent data words will follow
without a dummy zero bit. The READ instruction timing is
illustrated in Figure 3.
Erase/Write Enable and Disable
The device powers up in the write disable state. Any
writing after power−up or after an EWDS (erase/write
disable) instruction must first be preceded by the EWEN
(erase/write enable) instruction. Once the write instruction
is enabled, it will remain enabled until power to the device
is removed, or the EWDS instruction is sent. The EWDS
instruction can be used to disable all N93C66 write and erase
instructions, and will prevent any accidental writing or
clearing of the device. Data can be read normally from the
device regardless of the write enable/disable status. The
EWEN and EWDS instructions timing is shown in Figure 4.
t
SKLOW
t
CSH
t
DIH
VALID
t
PD0
, t
PD1
DATA VALID
t
CSMIN
Figure 2. Synchronous Data Timing
SK
CS
Don’t Care
A
N
DI
1
1
0
t
PD0
DO
HIGH−Z
A
N−1
A
0
Dummy 0
D
15 . . .
D
0
or
D
7 . . .
D
0
Address +
1
D
15 . . .
D
0
or
D
7 . . .
D
0
Address +
2
D
15 . . .
D
0
or
D
7 . . .
D
0
Address + n
D
15 . . .
or
D
7 . . .
Figure 3. READ Instruction Timing
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