S29WSxxxN MirrorBit™ Flash Family
S29WS256N, S29WS128N, S29WS064N
256/128/64 Megabit (16/8/4 M x 16-Bit) CMOS 1.8 Volt-only
Simultaneous Read/Write, Burst Mode Flash Memory
Data Sheet
PRELIMINARY
General Description
The Spansion S29WS256/128/064N are Mirrorbit
TM
Flash products fabricated on 110 nm process technology. These burst
mode Flash devices are capable of performing simultaneous read and write operations with zero latency on two separate
banks using separate data and address pins. They operate up to 80 MHz and use a single V
CC
of 1.7–1.95 volts that
makes them ideal for today’s demanding wireless applications requiring higher density, better performance and lowered
power consumption.
Distinctive Characteristics
Single 1.8 V read/program/erase (1.70–1.95 V)
110 nm MirrorBit™ Technology
Simultaneous Read/Write operation with zero
latency
32-word Write Buffer
Sixteen-bank architecture consisting of 16/8/4
Mbit for WS256N/128N/064N, respectively
Four 16 Kword sectors at both top and bottom of
memory array
254/126/62 64 Kword sectors (WS256N/128N/
064N)
Programmable burst read modes
— Linear for 32, 16 or 8 words linear read with or
without wrap-around
— Continuous sequential read mode
SecSi™ (Secured Silicon) Sector region consisting
of 128 words each for factory and customer
20-year data retention (typical)
Cycling Endurance: 100,000 cycles per sector
(typical)
RDY output indicates data available to system
Command set compatible with JEDEC standards
Hardware (WP#) protection of top and bottom
sectors
Dual boot sector configuration (top and bottom)
Offered Packages
— WS064N: 80-ball FBGA (7 mm x 9 mm)
— WS256N/128N: 84-ball FBGA (8 mm x 11.6 mm)
Low V
CC
write inhibit
Persistent and Password methods of Advanced
Sector Protection
Write operation status bits indicate program and
erase operation completion
Suspend and Resume commands for Program and
Erase operations
Unlock Bypass program command to reduce
programming time
Synchronous or Asynchronous program operation,
independent of burst control register settings
ACC input pin to reduce factory programming time
Support for Common Flash Interface (CFI)
Industrial Temperature range (contact factory)
Performance Characteristics
Read Access Times
Speed Option (MHz)
Max. Synch. Latency, ns (t
IACC
)
Max. Synch. Burst Access, ns (t
BACC
)
Max. Asynch. Access Time, ns (t
ACC
)
Max CE# Access Time, ns (t
CE
)
Max OE# Access Time, ns (t
OE
)
80
69
9
70
70
11.2
66
69
11.2
70
70
11.2
54
69
13.5
70
70
13.5
Current Consumption (typical values)
Continuous Burst Read @ 66 MHz
Simultaneous Operation (asynchronous)
Program (asynchronous)
Erase (asynchronous)
Standby Mode (asynchronous)
35 mA
50 mA
19 mA
19 mA
20 µA
Typical Program & Erase Times
Single Word Programming
Effective Write Buffer Programming (V
CC
) Per Word
Effective Write Buffer Programming (V
ACC
) Per Word
Sector Erase (16 Kword Sector)
Sector Erase (64 Kword Sector)
40 µs
9.4 µs
6 µs
150 ms
600 ms
Publication Number
S29WSxxxN_00
Revision
F
Amendment
0
Issue Date
October 29, 2004
P r e l i m i n a r y
Table of Contents
1. Ordering Information . . . . . . . . . . . . . . . . . . . . . .5
2. Input/Output Descriptions & Logic Symbol . . . .6
3. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
4. Physical Dimensions/Connection Diagrams . . . .8
4.1 Related Documents ........................................................................ 8
4.2 Special Handling Instructions for FBGA Package ................. 8
4.3 MCP Look-ahead Connection Diagram ................................. 13
5. Additional Resources . . . . . . . . . . . . . . . . . . . . . 15
6. Product Overview . . . . . . . . . . . . . . . . . . . . . . . . 16
6.1 Memory Map .................................................................................... 16
7. Device Operations . . . . . . . . . . . . . . . . . . . . . . . 19
7.1 Device Operation Table ............................................................... 19
7.2 Asynchronous Read ...................................................................... 19
7.3 Synchronous (Burst) Read Mode &
Configuration Register ........................................................................20
7.3.1 Continuous Burst Read Mode .......................................... 24
7.3.2 8-, 16-, 32-Word Linear Burst Read
with Wrap Around ....................................................................... 25
7.3.3 8-, 16-, 32-Word Linear Burst
without Wrap Around ................................................................ 25
7.3.4 Configuration Register ....................................................... 25
7.4 Autoselect ....................................................................................... 26
7.5 Program/Erase Operations ........................................................ 29
7.5.1. Single Word Programming ................................................ 29
7.5.2 Write Buffer Programming ................................................ 31
7.5.3 Sector Erase ........................................................................... 34
7.5.4 Chip Erase Command Sequence ..................................... 38
7.5.5 Erase Suspend/Erase Resume Commands ................... 38
7.5.6 Program Suspend/Program Resume Commands ....... 39
7.5.7 Accelerated Program/Chip Erase ...................................40
7.5.8 Unlock Bypass ........................................................................ 41
7.5.9 Write Operation Status ..................................................... 42
7.6 Simultaneous Read/Write ..........................................................48
7.7 Writing Commands/Command Sequences ..........................48
7.8 Handshaking ...................................................................................48
7.9 Hardware Reset ............................................................................ 49
7.10 Software Reset ............................................................................. 49
8. Advanced Sector Protection/Unprotection . . . 51
8.1 Lock Register .................................................................................. 52
8.2 Persistent Protection Bits .......................................................... 52
8.3 Dynamic Protection Bits .............................................................53
8.4 Persistent Protection Bit Lock Bit ...........................................53
8.5 Password Protection Method ...................................................54
8.6 Advanced Sector Protection Software Examples ...............56
8.7 Hardware Data Protection Methods ......................................56
8.7.1. WP# Method .........................................................................56
8.7.2 ACC Method .........................................................................56
8.7.3 Low V
CC
Write Inhibit .......................................................57
8.7.4 Write Pulse “Glitch Protection” .....................................57
8.7.5 Power-Up Write Inhibit .....................................................57
9. Power Conservation Modes . . . . . . . . . . . . . . . 58
9.1 Standby Mode ................................................................................. 58
9.2 Automatic Sleep Mode ............................................................... 58
9.3 Hardware RESET# Input Operation ...................................... 58
9.4 Output Disable (OE#) ................................................................ 58
10. SecSi
TM
(Secured Silicon) Sector Flash Memory
Region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
10.1 Factory SecSi
TM
Sector .................................................................59
10.2 Customer SecSi
TM
Sector .......................................................... 60
10.3 SecSi
TM
Sector Entry and SecSi Sector Exit
Command Sequences .......................................................................... 60
11. Electrical Specifications . . . . . . . . . . . . . . . . . . 62
11.1 Absolute Maximum Ratings ....................................................... 62
11.2 Operating Ranges ..........................................................................63
11.3 Test Conditions .............................................................................63
11.4 Key to Switching Waveforms ................................................. 64
11.5 Switching Waveforms ................................................................. 64
11.6 V
CC
Power-up .............................................................................. 64
11.7 DC Characteristics (CMOS Compatible) .............................65
11.8 AC Characteristics ...................................................................... 66
11.8.1. CLK Characterization ....................................................... 66
11.8.2 Synchronous/Burst Read ...................................................67
11.8.3 Timing Diagrams ................................................................. 68
11.8.4 AC Characteristics—Asynchronous Read ................. 70
11.8.5 Hardware Reset (RESET#) ..............................................72
11.8.6 Erase/Program Timing ........................................................73
11.8.7 Erase and Programming Performance ...........................83
11.8.8 BGA Ball Capacitance ....................................................... 84
12. Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
12.1 Common Flash Memory Interface ..........................................88
13. Commonly Used Terms . . . . . . . . . . . . . . . . . . 92
14. Revisions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
2
S29WSxxxN MirrorBit™ Flash Family
S29WSxxxN_00F0 October 29, 2004
P r e l i m i n a r y
List of Figures
Figure 4.2. VBH084—84-ball Fine-Pitch Ball Grid Array (FBGA) 8 x 11.6 mm MCP Compatible Package .......................................................... 10
Figure 4.3. 80-ball Fine-Pitch Ball Grid Array (S29WS064N) .................................................................................................................... 11
Figure 4.4. TLC080—80-ball Fine-Pitch Ball Grid Array (FBGA) 7 x 9 mm MCP Compatible Package ............................................................... 12
Figure 4.5. MCP Look-ahead Diagram ................................................................................................................................................... 14
Figure 7.2. Synchronous Read ............................................................................................................................................................. 24
Figure 7.19. Single Word Program....................................................................................................................................................... 30
Figure 7.22. Write Buffer Programming Operation ................................................................................................................................. 34
Figure 7.24. Sector Erase Operation.................................................................................................................................................... 37
Figure 7.33. Write Operation Status Flowchart ...................................................................................................................................... 44
Figure 8.2. Lock Register Program Algorithm ......................................................................................................................................... 55
Figure 11.2. Maximum Positive Overshoot Waveform.............................................................................................................................. 62
Figure 11.3. Test Setup ...................................................................................................................................................................... 63
Figure 11.4. Input Waveforms and Measurement Levels.......................................................................................................................... 64
Figure 11.5. V
CC
Power-up Diagram ..................................................................................................................................................... 64
Figure 11.6. CLK Characterization ........................................................................................................................................................ 66
Figure 11.7. CLK Synchronous Burst Mode Read .................................................................................................................................... 68
Figure 11.8. 8-word Linear Burst with Wrap Around ............................................................................................................................... 69
Figure 11.9. 8-word Linear Burst without Wrap Around ........................................................................................................................... 69
Figure 11.10. Linear Burst with RDY Set One Cycle Before Data ............................................................................................................... 70
Figure 11.11. Asynchronous Mode Read................................................................................................................................................ 71
Figure 11.12. Reset Timings................................................................................................................................................................ 72
Figure 11.2. Chip/Sector Erase Operation Timings: WE# Latched Addresses ............................................................................................. 74
Figure 11.13. Asynchronous Program Operation Timings: WE# Latched Addresses ..................................................................................... 75
Figure 11.14. Synchronous Program Operation Timings: CLK Latched Addresses ........................................................................................ 76
Figure 11.15. Accelerated Unlock Bypass Programming Timing ................................................................................................................ 77
Figure 11.16. Data# Polling Timings (During Embedded Algorithm) .......................................................................................................... 77
Figure 11.17. Toggle Bit Timings (During Embedded Algorithm) ............................................................................................................... 78
Figure 11.18. Synchronous Data Polling Timings/Toggle Bit Timings ......................................................................................................... 78
Figure 11.19. DQ2 vs. DQ6 ................................................................................................................................................................. 79
Figure 11.20. Latency with Boundary Crossing when Frequency > 66 MHz................................................................................................. 79
Figure 11.21. Latency with Boundary Crossing into Program/Erase Bank ................................................................................................... 80
Figure 11.22. Example of Wait States Insertion ..................................................................................................................................... 81
Figure 11.23. Back-to-Back Read/Write Cycle Timings ............................................................................................................................ 82
October 29, 2004 S29WSxxxN_00_F0
S29WSxxxN MirrorBit™ Flash Family
3
P r e l i m i n a r y
List of Tables
Read Access Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Current Consumption (typical values) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Typical Program & Erase Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Table 2.1. Input/Output Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Table 6.1. S29WS256N Sector & Memory Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 6.2. S29WS128N Sector & Memory Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 6.3. S29WS064N Sector & Memory Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 7.4. Device Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 7.5. Address Latency for x Wait States (≤ 80 MHz, WS256N only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Table 7.6. Address Latency for 6 Wait States (≤ 80 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Table 7.7. Address Latency for 5 Wait States (≤ 68 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Table 7.8. Address Latency for 4 Wait States (≤ 54 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Table 7.9. Address Latency for 3 Wait States (≤ 40 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Table 7.10. Address/Boundary Crossing Latency for 6 Wait States (≤ 80 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 7.11. Address/Boundary Crossing Latency for 5 Wait States (≤ 68 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 7.12. Address/Boundary Crossing Latency for 4 Wait States (≤ 54 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 7.13. Address/Boundary Crossing Latency for 3 Wait States (≤ 40 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 7.14. Burst Address Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 7.15. Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 7.16. Autoselect Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 7.17. Autoselect Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 7.18. Autoselect Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Table 7.20. Single Word Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 7.21. Write Buffer Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 7.23. Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 7.25. Chip Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 7.26. Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Table 7.27. Erase Resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Table 7.28. Program Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Table 7.29. Program Resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 7.30. Unlock Bypass Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Table 7.31. Unlock Bypass Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Table 7.32. Unlock Bypass Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 7.34. DQ6 and DQ2 Indications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 7.35. Write Operation Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 7.36. Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Table 8.1. Lock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 8.2. Sector Protection Schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 10.1. SecSi
TM
Sector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 10.2. SecSi Sector Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Table 10.3. SecSi Sector Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 10.4. SecSi Sector Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Table 11.1. Test Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Table 12.1. Memory Array Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 12.2. Sector Protection Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
Table 12.3. CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 12.4. System Interface String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
Table 12.5. Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 12.6. Primary Vendor-Specific Extended Query . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
4
S29WSxxxN MirrorBit™ Flash Family
S29WSxxxN_00_F0 October 29, 2004
P r e l i m i n a r y
1
Ordering Information
The ordering part number is formed by a valid combination of the following:
256
N
0S
BA
W
01
0
PACKING TYPE
0
= Tray (standard; see note 1)
2
= 7-inch Tape and Reel
3
= 13-inch Tape and Reel
MODEL NUMBER (Note 3)
(Package Ball Count, Package Dimensions, DYB Protect/Unprotect After
Power-up)
01
= 84-ball, 8 x 11.6 mm, DYB Unprotect
11
= 80-ball, 7 x 9 mm, DYB Protect
TEMPERATURE RANGE (Note 3)
W
= Wireless (–25°C to +85°C)
I
= Industrial (–40°C to +85°C, contact factory for availability)
PACKAGE TYPE AND MATERIAL
BA
= Very Thin Fine-Pitch BGA, Lead (Pb)-free Compliant Package
BF
= Very Thin Fine-Pitch BGA, Lead (Pb)-free Package
SPEED OPTION (BURST FREQUENCY)
0S
= 80 MHz
0P
= 66 MHz
0L
= 54 MHz
PROCESS TECHNOLOGY
N
= 110 nm MirrorBit™ Technology
FLASH DENSITY
256
= 256 Mb
128
= 128 Mb
064
= 64 Mb
DEVICE FAMILY
S29WS = 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory
S29WS
S29WSxxxN Valid Combinations (Notes 1, 2, 3)
Base Ordering
Part Number
S29WS256N
BAW (Lead (Pb)-free Compliant),
BFW (Lead (Pb)-free)
Speed
Option
Package Type, Material, &
Temperature Range
Model
Number
01
11
0S, 0P, 0L
01
11
01
11
0, 2, 3
(Note 1)
1.70–1.95 V
Packing
Type
V
IO
Range
DYB
Power Up
State
Unprotect
Protect
Unprotect
Protect
Unprotect
Protect
Package Type
(Note 2)
S29WS128N
8 mm x 11.6 mm
84-ball
MCP-Compatible
7 mm x 9 mm
80-ball
MCP-Compatible
S29WS064N
Notes:
1. Type 0 is standard. Specify other options as required.
2. BGA package marking omits leading “S29” and packing type
designator from ordering part number.
3. For 1.5 V
IO
option, other boot options, or industrial temperature
range, contact your local sales office.
Valid Combinations
Valid Combinations list configurations planned to be supported in vol-
ume for this device. Consult your local sales office to confirm avail-
ability of specific valid combinations and to check on newly released
combinations.
October 29, 2004 S29WSxxxN_00_F0
S29WSxxxN MirrorBit™ Flash Family
5
Renesas Electronics MCUs
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