VersaClock
®
Programmable Clock Generator
5P35023
DATASHEET
Description
The 5P35023 is a VersaClock programmable clock generator
and is designed for low-power, consumer, and
high-performance PCI Express applications. The 5P35023
device is a three PLL architecture design, and each PLL is
individually programmable and allowing for up to six unique
frequency outputs.
The 5P35023 has built-in unique features such as Proactive
Power Saving (PPS), Performance-Power Balancing (PPB),
Overshot Reduction Technology (ORT) and Extreme Low
Power DCO. An internal OTP memory allows the user to store
the configuration in the device. After power up, the user can
change the device register settings through the I
2
C interface
when I
2
C mode is selected.
The device has programmable VCO and PLL source selection
to allow the user to do power-performance optimization based
on the application requirements. It also supports three
single-ended outputs and two pair of differential outputs that
support LVCMOS, LVPECL, LVDS and LPHCSL. A Low
Power 32.768kHz clock is supported with only less than 2µA
current consumption for system RTC reference clock.
Features
•
Configurable OE pin function as OE, PD#, PPS or DFC
•
•
•
•
•
•
•
control function
Configurable PLL bandwidth/minimizes jitter peaking
PPS: Proactive Power Saving features save power during
the end device power down mode
PPB: Performance Power Balancing feature allows
minimum power consumption base on required
performance
DFC: Dynamic Frequency Control feature allows user to
dynamically switch between and up to 4 difference
frequencies smoothly
Two PLLs support independent Spread Spectrum clocks to
lower system EMI
Store user configuration into OTP memory
I
2
C interface
Key Specifications
•
PCIe clocks phase jitter: PCIe Gen3
•
Differential clocks < 1.5 ps rms jitter integer range 12kHz–
20MHz
Typical Applications
•
PCIe Gen1/2/3 clock generator
•
Consumer application crystal replacements
•
SmartDevice, Handheld, Computing and Consumer
applications
Output Features
•
2 DIFF outputs with configurable LPHSCL, LVDS,
•
•
•
LVPECL, LVCMOS output pairs. 1MHz–500MHz (160MHz/
with LVCMOS mode)
3 LVCMOS outputs: 1MHz–160MHz
Maximum 8 LVCMOS outputs as REF + 3 × SE + 2 ×
DIFF_T/C as LVCMOS
Low Power 32.768kHz clock supported for all SE1–SE3
Pin Assignment
VDDDIFF2
VDDSE3
20
DIFF2B
DIFF2
OE3
24
23
22
21
SE3
19
18
17
16
VDDA
SDA_DFCO
SEL_DFC/SCL_DFC1
CLKIN/X2
CLKINB/X1
VBAT
1
2
3
DIFF1
DIFF1B
VDDDIFF1
OE1
SE1
VDDSE1
5P35023
4
5
6
7
8
9
10
11
12
15
14
13
NC
REF
OE2
VDD33
24-pin VFQFPN
5P35023 NOVEMBER 30, 2017
1
VDDSE2
SE2
©2017 Integrated Device Technology, Inc.
5P35023 DATASHEET
Functional Block Diagram
DIV 1/REF
OSC
MUX
DIV 1
DIV 3
MUX
CLKINB/X1
CLKIN/X2
PLL1
DIV 2
DIV 1/REF
DIV 3
MUX
VDDDIFF2
DIFF2
DIFF2B
VDDDIFF1
DIFF1
DIFF1B
OE3
SE3
VDDSE3
OE2
SE2
VDDSE2
OE1
SE1
VDDSE1
REF
DIV 2
VBAT
VDD33
Power
Monitor
POR
MUX
PLL2
MUX
DIV 3
DIV 4/REF
32K
MUX
MUX
DIV 4
DIV 4/REF
DIV 5
32K
MUX
VDDA
MUX
PLL3
DIV 5
DIV 4/REF
DIV 5
32K
MUX
VSS
Calibration
32.768K
DCO
SCL_DFC1
SDA_DFC0
I2C Engine
Overshoot Reduction
(ORT)
Dynamic Frequency Control Logic (DFC)
OTP memory (1 configuration )
Proactive Power Saving Logic (PPS)
Timer
Power Group
Power supply table
VDDSE1
SE
SE1
DIFF
DIV
MUX
PLL
DCO
REF
Xtal
SE2*
VDDSE2
SE3*
VDDSE3
DIFF1
DIV3/4
MUXPLL2 PLL2
VDDDIFF1
DIFF2
DIV1
MUXPLL1
VDDDIFF2
DIV5
PLL3
DCO
REF
Xtal
VDD33
DCO
Xtal
VBAT
DIV2
PLL1
VDDA
* VDDSEx for non-32kHz outputs should be OFF when VDDA/VDD3 turn OFF, VBAT mode only support
32.768kHz outputs from SE1-3.
* SE2 & SE3 only available in 5P35023.
* VBAT power ramp up should be same or earlier than other VDD power rail.
Output Source Table
Source
Xtal REF
32.768KHz
PLL1
PLL2
PLL3
Outputs
REF
Xtal REF
SE1
Xtal REF
32.768KHz
PLL2
PLL3
SE2*
Xtal REF
32.768KHz
PLL2
PLL3
SE3*
Xtal REF
32.768KHz
PLL1
PLL2
DIFF1
DIFF2
PLL1
PLL2
PLL3
PLL1
PLL2
PLL3
* SE2 & SE3 only available in 5P35023
VERSACLOCK
®
PROGRAMMABLE CLOCK GENERATOR
2
NOVEMBER 30, 2017
5P35023 DATASHEET
Output Source Selection Register Setting Table
SE1
From
From
From
From
32K
PLL3 + Divider 5
PLL2 + Divider 4
REF + Divider 4
SE2 (5P35023)
32K
PLL3 + Divider 5
PLL2 + Divider 4
REF + Divider 4
SE3 (5P35023)
32K
PLL1 + Divider 2
PLL2 + Divider 4
REF + Divider 4
B36<4>
0
1
1
1
B31<7>
0
1
1
1
B33<7>
0
1
1
1
B34<7>
0
1
0
B35<7>
0
1
0
B36<3>
1
0
1
1
B31<6>
0
0
1
1
B33<6>
0
0
1
1
B0<3>
0
0
1
B0<3>
0
0
1
B31<1>
0
0
1
0
B36<0>
0
0
1
1
B7<5>
0
1
0
0
B29<3>
0
0
0
1
B31<1>
0
0
1
0
B29<3>
0
0
0
1
B29<3>
0
0
0
1
B36<1>
0
0
1
1
B31<1>
0
0
1
0
From
From
From
From
From
From
From
From
DIFF1
From PLL1 + Divider 1
From PLL2/3 + Divider 3
From REF + Divider 1
DIFF2
From PLL1 + Divider 1
From PLL2/3 + Divider 3
From REF + Divider 1
Glossary of Features
Term
DFC
ORT
Function Description
Dynamic Frequency Control, from selected PLL to support four VCO frequencies,
means two different output frequencies by assign H/W pin state changes
Overshoot Reduction, when the DFC dynamic frequency change is functional, the
VCO change frequency smoothly to target frequency without overshoot or under
shoot.
Output Enable function, each output can be controlled by assigned OE pin, the
dedicated OE pin can be OTP programmable as Global Power Down function (PD#)
or Output enable (OE) or proactive power saving function (PPS) or RESET pin
function.
Spread Spectrum clock
LVCMOS outputs with slew rate control - slow and fast.
Proactive Power Saving, utilize OE pin as monitor pin for end device X2 clock status,
details see PPS function description
Apply to
PLL2
PLL2
OE
SS
Slew Rate
PPS
OE1~3
PLL1/PLL2
LVCMOS
SE1~3
NOVEMBER 30, 2017
3
VERSACLOCK
®
PROGRAMMABLE CLOCK GENERATOR
5P35023 DATASHEET
Pin Descriptions
Number
1
2
3
Name
VDDA
SDA_DFC0
SEL_DFC/SCL_DFC1
Type
Power
I/O
Input
Description
VDD 3.3V
I2C DATA pin, the pin can be DFC0 function by pin3 SEL_DFC power on latch status
I2C CLK pin,
SEL_DFC is a latch input pin during the power up
High on power on: I2C mode as SCLK function,
Low on power on: pin3 SCL and pin2 SDA as DFC function control pins.
Crystal Oscillator output or Differential clock input pin (CLKIN)
Crystal Oscillator input or Differential clock input pin (CLKINB) or single-ended clock input
Power supply pin for 32.768KHz DCO, usually connect to coin cell battery, 3.0~3.3V
NC
3.3V Reference clock output
VDD 3.3V
Output enable control 2, multi-function pin. Refer to OE function table.
Output power supply. Connect to 1.8 to 3.3V. Sets output voltage levels for SE2.
Output Clock SE2.
Output power supply. Connect to 1.8 to 3.3V. Sets output voltage levels for SE1.
Output Clock SE1.
Function selected from OTP preprogram register bits.
Apply a pull-up to 6.5V when burn OTP registers.
Refer to OE function table for details
Output power supply. Connect to 2.5 to 3.3V. Sets output voltage levels for DIFF1.
Differential clock output 1_Complement,
can be OTP pre-program to LVCMOS/LPHCSL/LVDS/LVPECL output type
Differential clock output 1_True,
can be OTP pre-program to LVCMOS/LPHCSL/LVDS/LVPECL output type
Output Clock SE3.
Output power supply. Connect to 1.8 to 3.3V. Sets output voltage levels for SE3.
Output enable control 3, multi-function pin. Refer to OE function table.
Output power supply. Connect to 2.5 to 3.3V. Sets output voltage levels for DIFF2.
Differential clock output 2_Complement,
can be OTP pre-program to LVCMOS/LPHCSL/LVDS/LVPECL output type
Differential clock output 2_True,
can be OTP pre-program to LVCMOS/LPHCSL/LVDS/LVPECL output type
Connect to ground pad.
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
ePAD
CLKIN/X2
CLKINB/X1
VBAT
NC
REF
VDD33
OE2
VDDSE2
SE2
VDDSE1
SE1
OE1
VDDDIFF1
DIFF1B
DIFF1
SE3
VDDSE3
OE3
VDDDIFF2
DIFF2B
DIFF2
I/O
Input
Power
NC
Output
Power
Input
Power
Output
Power
Output
Input
Power
Output
Output
Output
Power
Input
Power
Output
Output
Power
VERSACLOCK
®
PROGRAMMABLE CLOCK GENERATOR
4
NOVEMBER 30, 2017
5P35023 DATASHEET
Device Feature and Function
DFC–Dynamic Frequency Control
•
OTP program (only) setup 4 different feedback fractional divider (4 VCO frequencies) that apply to PLL2.
•
ORT (overshoot reduction) function will be applied automatically during the VCO frequency change.
•
Smooth frequency incremental or decremental from current VCO to targeted VCO base on DFC hardware pins selection.
DFC Block Diagram
M divider
PLL
OUT DIV
Selector
00
01
10
11
DFC1:0
N divider
N divider
N divider
N divider
OTP/I2C
DFC Function Priority Table
DFC_EN
bit(W32[4])
0
1
1
1
1
1
OE1_fun_sel
(W30[6:5])
x
11 (DFC)
11 (DFC)
00~10
00~10
00~10
OE3_fun_sel
(W30[3:2])
x
00~10 (DFC)
11 (DFC)
11
00~10
00~10
SCL_DFC1
x
x
x
x
0
1
DFC[1:0]
0
[0,OE1]
[OE3,OE1]
Not permit
[SCL_DFC1,
SDA_DFC0]
W30[1:0]
Notes
DFC disable
One pin DFC -
OE1
Two pin DFC -
OE3,OE1
Not supported
I2C pin as DFC
control pins mode
I2C control DFC
mode
DFC Function Programming
•
Register B63b3:2 select DFC00–DFC11 configuration.
•
Byte16–19 are the register for PLL2 VCO setting, base on B63b3:2 configuration selection, the data write to B16–19 will be
•
•
store in selected.
Refer to DFC function priority table, select proper control pin(s) to activate DFC function.
Note the DFC function can also be controlled by I2C access.
NOVEMBER 30, 2017
5
VERSACLOCK
®
PROGRAMMABLE CLOCK GENERATOR
Embedded System
京公网安备 11010802033920号
EEWORLD
