*Product capability established by initial characterization. The
“EH” version is acceptance tested on a wafer-by-wafer basis to
50krad(Si) at low dose rate.
Applications
• LDO regulator for space application
• DSP, FPGA, and µP core power supplies
• Post-regulation of switched mode power supplies
• Down-hole drilling
Related Literature
• For a full list of related documents please visit our website
-
ISL75051SEH
and
ISL75051SRH
product pages
EN
0.30
DROPOUT VOLTAGE (V)
ROCP
EN
OCP
BYP
ADJ
VOUT
GND
R
1
0.1µF 220µF
VIN
2.67k
0.1µF
VOUT
+150°C
0.25
0.20
0.15
0.10
0.05
0.00
0.00
+125°C
VIN
VIN
PG
220µF
0.1µF
ISL75051SEH
+25°C
4.7nF
PG
R
2
100pF
0.50
1.00
1.50
2.00
I
OUT
(A)
2.50
3.00
3.50
FIGURE 1. TYPICAL APPLICATION
FIGURE 2. DROPOUT vs I
OUT
FN8294 Rev.7.00
May 22, 2017
Page 1 of 23
ISL75051SEH, ISL75051SRH
Block Diagram
VIN
CURRENT
LIMIT ADJ
520MV
BYPASS
REFERENCE
BIAS
CURRENT
LIMIT
THERMAL
SHUTDOWN
POWER
PMOS
OCP
VOUT
ENABLE
LEVEL
SHIFT
ADJ
VADJ
PGOOD
DELAY
450mV
GND
FIGURE 3. BLOCK DIAGRAM
Typical Application
EN
EN
511
OCP
VIN
VIN
VIN
VIN
VIN
VIN
VIN
PG
220µF
0.1µF
4.32k
2.67k
17
18
2
1
VOUT
GND
0.1µF
220µF
11
12
13
8
7
6
ADJ
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
0.2µF
10
9
BYP
14
5
ISL75051SxH
15
16
4
3
4.7n
VIN
2.26k
5.49k
100pF
PG
FIGURE 4. TYPICAL APPLICATION
FN8294 Rev.7.00
May 22, 2017
Page 2 of 23
ISL75051SEH, ISL75051SRH
Pin Configuration
ISL75051SEH, ISL75051SRH
(18 LD CDFP)
TOP VIEW
GND
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VADJ
BYP
1
2
3
4
5
6
7
8
9
GND
18
17
16
15
14
13
12
11
10
PG
VIN
VIN
VIN
VIN
VIN
VIN
OCP
EN
NOTE: The ESD triangular mark is indicative of pin #1. It is a part of the device
marking and is placed on the lid in the quadrant where pin #1 is located.
Pin Descriptions
PIN NUMBER
12, 13, 14
15, 16, 17
18
1
2, 3, 4
5, 6, 7
8
9
10
11
Top Lid
PIN NAME
VIN
PG
GND
VOUT
VADJ
BYP
EN
OCP
GND
Input supply pins.
V
OUT
in regulation signal. Logic low defines when V
OUT
is not in regulation. Must be grounded if not used.
GND pin.
Output voltage pins.
VADJ pin allows V
OUT
to be programmed with an external resistor divider.
To filter the internal reference, connect a 0.1µF capacitor from BYP pin to GND.
VIN independent chip enable. TTL and CMOS compatible.
Allows current limit to be programmed with an external resistor.
The top lid is connected to GND pin of the package.
DESCRIPTION
FN8294 Rev.7.00
May 22, 2017
Page 3 of 23
ISL75051SEH, ISL75051SRH
Ordering Information
ORDERING NUMBER
(Notes
1, 2)
5962R1121202VXC
5962R1121202V9A
5962R1121202VYC
N/A
N/A
5962R1121201VXC
5962R1121201QXC
5962R1121201V9A
N/A
N/A
N/A
NOTES:
1. These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations.
2. Specifications for Rad Hard QML devices are controlled by the Defense Logistics Agency Land and Maritime (DLA). The SMD numbers listed must be
used when ordering.
3. The /PROTO and /SAMPLE are not rated or certified for Total Ionizing Dose (TID) or Single Event Effect (SEE) immunity. These parts are intended for
engineering evaluation purposes only. The /PROTO parts meet the electrical limits and conditions across the temperature range specified in the DLA
SMD and are in the same form and fit as the qualified device. The /SAMPLE die is capable of meeting the electrical limits and conditions specified
in the DLA SMD at +25°C only. The /SAMPLE is a die and does not receive 100% screening across the temperature range to the DLA SMD electrical
limits. These part types do not come with a certificate of conformance because there is no radiation assurance testing and they are not DLA qualified
devices.
4. Evaluation board uses the /PROTO parts. The /PROTO parts are not rated or certified for Total Ionizing Dose (TID) or Single Event Effect (SEE) immunity.
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
5. Extended operation at these conditions may compromise reliability. Exceeding these limits will result in damage. Recommended operating conditions
define limits where specifications are guaranteed.
6. Refer to
“Thermal Guidelines” on page 17.
7. Product capability established by initial characterization. The "EH" version is acceptance tested on a wafer-by-wafer basis to 50krad(Si) at low dose
rate.
8. Specify EVAL test conditions for SET/SEB/SEL here.
9.
JA
is measured in free air with the component mounted on a high-effective thermal conductivity test board with “direct attach” features. See Tech
Brief
TB379.
10. For
JC
, the “case temp” location is the center of the package underside.
11. The device can work down to V
OUT
= 0.8V; however, the SET performance of <±5% at LET = 86MeV•cm
2
/mg is established at V
OUT
= >1.5V only.
SET tests performed with 220µF, 10V, 25mΩ, and 0.1µF CDR04 capacitor on the input and output.
Electrical Specifications
Unless otherwise noted, all parameters are established over the following specified conditions: V
IN
= V
OUT
+
0.4V, V
OUT
= 1.8V, C
IN
= C
OUT
= 220µF, 25mΩ, and 0.1µF X7R, T
J
= +25°C, I
L
= 0A. Applications must follow thermal guidelines of the package to
determine worst-case junction temperature (see
Note 15).
Boldface limits apply across the operating temperature range, -55°C to +125°C. Pulse load
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