MCP19122/3
Digitally Enhanced Power Analog Controller
with Integrated Synchronous Driver
Synchronous Buck Features
• Input Voltage: 4.5V to 40V (operating), 48V
(non-operating)
• Output Voltage: 0.3V to 16V
- 0.1% typical output voltage accuracy
- Greater than 16V requires external divider
• Switching Frequency: 100 kHz to 1.6 MHz
• Shutdown Quiescent Current: 50 µA Typical
• High-Drive:
- +5V Gate Drive
- 2A Source Current
- 2A Sink Current
• Low-Drive:
- +5V Gate Drive
- 2A Source Current
- 4A Sink Current
• Emulated Average Current Mode Control
• Differential Remote Output Sense
• Multi-Phase Systems:
- Master or Slave
- Frequency Synchronized
- Common Current Sense Signal
• Multiple Output Systems:
- Master or Slave
- Frequency Synchronized
• AEC-Q100 Qualified
• Configureable Parameters:
- Overcurrent Limit
- Input Undervoltage Lockout
- Input Overvoltage
- Output Overvoltage
- Output Undervoltage
- Internal Analog Compensation
- Soft Start Profile
- Synchronous Driver Dead Time
- Switching Frequency
• Thermal Shutdown
Microcontroller Features
• Precision 8 MHz Internal Oscillator Block:
- Factory Calibrated
• Interrupt Capable
- Firmware
- Interrupt-on-Change Pins
• Only 35 Instructions to Learn
• 4096 Words On-Chip Program Memory
• High Endurance Flash:
- 100,000 Write Flash Endurance
- Flash Retention: >40 years
• Watchdog Timer (WDT) with Independent
Oscillator for Reliable Operation
• Programmable Code Protection
• In-Circuit Debug (ICD) via Two Pins (MCP19123)
• In-Circuit Serial Programming™ (ICSP™) via Two
Pins
• 12 I/O Pins and One Input-Only Pin (MCP19122)
- 3 Open Drain Pins
- 2 Weak Current Source Pins
• 16 I/O Pins and One Input-Only Pin (MCP19123)
- 3 Open Drain Pins
- 2 Weak Current Source Pins
• Analog-to-Digital Converter (ADC):
- 10-bit Resolution
- 24 Internal Channels
- 8 External Channels
• Timer0: 8-bit Timer/Counter with 8-Bit Prescaler
• Enhanced Timer1:
- 16-bit Timer/Counter with Prescaler
- 2 Selectable Clock Sources
- External Gate Input Mode
• Timer2: 8-Bit Timer/Counter with Prescaler
- 8-bit Period Register
• Capture, Compare Module
• I
2
C
TM
Communication:
- 7-bit Address Masking
- 2 Dedicated Address Registers
- SMBus/PMBus
TM
Compatibility
2017 Microchip Technology Inc.
DS20005750A-page 1
MCP19122/3
TABLE 1:
24-Pin QFN
24-PIN QFN (MCP19122) SUMMARY
Interrupt
Pull-up
ANSEL
Timers
MSSP
A/D
I/O
Basic
Additional
GPA0
GPA1
GPA2
GPA3
GPA4
GPA5
GPA6
GPA7
GPB0
GPB1
GPB2
GPB3
V
IN
V
DD
GND
P
GND
LDRV
HDRV
PHASE
BOOT
+V
SEN
–V
SEN
ISP
ISN
EP
Note 1:
2:
3:
4:
5:
1
2
3
4
8
7
6
5
22
23
24
21
19
20
9
14
15
17
16
18
11
10
13
12
—
Y
Y
Y
Y
N
N
N
N
N
Y
Y
N
N
N
N
N
N
N
N
N
N
N
N
N
—
AN0
AN1
AN2
AN3
—
—
—
—
—
AN4
AN5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
T0CKI
—
—
—
—
IOC
IOC
IOC
INT
IOC
IOC
IOC
(4)
IOC
IOC
IOC
IOC
IOC
IOC
—
—
—
—
—
—
—
—
—
—
—
—
—
Y
Y
—
—
N
Y
(5)
N
N
N
Y
Y
Y
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
MCLR
ICSPDAT
ICSPCLK
—
—
—
—
V
IN
V
DD
GND
—
—
—
—
—
—
—
—
—
—
Analog Debug Output
(1)
Sync Signal In/Out
(2,
3)
Weak Current Source
Weak Current Source
Timer1 Gate Input 1
—
—
—
—
—
Current Sense Output
Current Reference Input
(3)
Timer1 Gate Input 2
Clock Signal In/Out
(2,
3)
Device Input Voltage
Internal Regulator Output
Small Signal Ground
Large Signal Ground
Low-Side MOSFET
Connection
High-Side MOSFET
Connection
Switch Node
Floating Bootstrap Supply
Output Voltage
Differential Sense
Output Voltage
Differential Sense
Current Sense Input
Current Sense Input
Exposed Pad
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SCL
SDA
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
The Analog Debug Output is selected when the BUFFCON<BNCHEN> bit is set.
Selected when device is functioning as multiple output master or slave by proper configuration of the MSC<2:0> bits in
the MODECON register.
Selected when device is functioning as multi-phase master or slave by proper configuration of the MSC<2:0> bits in the
MODECON register.
The IOC is disabled when MCLR is enabled.
Weak pull-up always enabled when MCLR is enabled, otherwise the pull-up is under user control.
2017 Microchip Technology Inc.
DS20005750A-page 3
MCP19122/3
TABLE 2:
28-Pin QFN
28-PIN QFN (MCP19123) SUMMARY
Interrupt
Pull-up
ANSEL
Timers
MSSP
A/D
I/O
Basic
Additional
GPA0
GPA1
GPA2
GPA3
GPA4
GPA5
GPA6
GPA7
GPB0
GPB1
GPB2
GPB3
GPB4
GPB5
GPB6
GPB7
V
IN
V
DD
GND
P
GND
LDRV
HDRV
PHASE
BOOT
+V
SEN
–V
SEN
ISP
ISN
EP
Note 1:
2:
3:
4:
5:
1
2
3
5
9
8
7
6
24
26
28
23
4
27
10
25
21
22
11
16
17
19
18
20
13
12
15
14
—
Y
Y
Y
Y
N
N
N
N
N
Y
Y
N
Y
Y
N
N
N
N
N
N
N
N
N
N
N
N
N
N
—
AN0
AN1
AN2
AN3
—
—
—
—
—
AN4
AN5
—
AN6
AN7
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
T0CKI
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SCL
SDA
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
IOC
IOC
IOC
INT
IOC
IOC
IOC
(4)
IOC
IOC
IOC
IOC
IOC
IOC
IOC
IOC
IOC
IOC
—
—
—
—
—
—
—
—
—
—
—
—
—
Y
Y
Y
Y
N
Y
(5)
N
N
N
Y
Y
Y
Y
Y
Y
Y
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
MCLR
—
—
—
—
—
—
ICSPDAT
ICDDAT
ICSPCLK
ICDCLK
—
—
V
IN
V
DD
GND
—
—
—
—
—
—
—
—
—
—
Analog Debug Output
(1)
Sync Signal In/Out
(2,
3)
Weak Current Source
Weak Current Source
Timer1 Gate Input 1
—
—
CCD Input 1
—
—
Current Sense Output
Current Reference Input
(3)
Timer1 Gate Input 2
Clock Signal In/Out
(2,
3)
—
—
CCD Input 2
External A/D Reference
Device Input Voltage
Internal Regulator Output
Small Signal Ground
Large Signal Ground
Low-Side MOSFET
Connection
High-Side MOSFET
Connection
Switch Node
Floating Bootstrap Supply
Output Voltage
Differential Sense
Output Voltage
Differential Sense
Current Sense Input
Current Sense Input
Exposed Pad
The Analog Debug Output is selected when the BUFFCON<BNCHEN> bit is set.
Selected when device is functioning as multiple output master or slave by proper configuration of the MSC<2:0> bits in
the MODECON register.
Selected when device is functioning as multi-phase master or slave by proper configuration of the MSC<2:0> bits in the
MODECON register.
The IOC is disabled when MCLR is enabled.
Weak pull-up always enabled when MCLR is enabled, otherwise the pull-up is under user control.
2017 Microchip Technology Inc.
DS20005750A-page 5