PIC24FJ256GB406T-I/MR datasheet, PDF

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PIC24FJ256GB406T-I/MR: Description16-bit Microcontroller - MCU 16 Bit MCU, 16 MIPS 256KB Flash XLP, USB; CategoryThe embedded processor and controller Microcontrollers and processors; File Size4MB，559 Pages; ManufacturerMicrochip; Websitehttps://www.microchip.com; Environmental Compliance

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PIC24FJ256GB406T-I/MR Overview

16-bit Microcontroller - MCU 16 Bit MCU, 16 MIPS 256KB Flash XLP, USB

PIC24FJ256GB406T-I/MR Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Microchip
package instruction	QFN-64
Reach Compliance Code	compliant
Has ADC	YES
Address bus width
bit size	16
CPU series	PIC24
maximum clock frequency	32 MHz
DAC channel	YES
DMA channel	YES
External data bus width
JESD-30 code	S-PQCC-N64
JESD-609 code	e3
length	9 mm
Number of DMA channels	6
Number of I/O lines	52
Number of terminals	64
Number of timers	19
On-chip data RAM width	16
On-chip program ROM width	24
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
PWM channel	YES
Package body material	PLASTIC/EPOXY
encapsulated code	VQCCN
Encapsulate equivalent code	LCC64,.35SQ,20
Package shape	SQUARE
Package form	CHIP CARRIER, VERY THIN PROFILE
RAM (bytes)	16384
RAM (number of words)	8192
rom(word)	88064
ROM programmability	FLASH
Maximum seat height	1 mm
speed	32 MHz
Maximum supply voltage	3.6 V
Minimum supply voltage	2 V
Nominal supply voltage	3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Matte Tin (Sn) - annealed
Terminal form	NO LEAD
Terminal pitch	0.5 mm
Terminal location	QUAD
width	9 mm
uPs/uCs/peripheral integrated circuit type	MICROCONTROLLER

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PIC24FJ256GA412/GB412 FAMILY

16-Bit Flash Microcontrollers with Dual Partition Flash Memory,

XLP, LCD, Cryptographic Engine and USB On-The-Go

Extreme Low-Power Features

• Multiple Power Management Options for Extreme Power

Reduction:

- V

BAT

allows for lowest power consumption on backup

battery (with or without RTCC)

- Deep Sleep allows near total power-down with the ability to

wake-up on external triggers

- Sleep and Idle modes selectively shut down peripherals

and/or core for substantial power reduction and fast wake-up

- Doze mode allows CPU to run at a lower clock speed than

peripherals

• Alternate Clock modes allow On-the-Fly Switching to a Lower

Clock Speed for Selective Power Reduction

• Extreme Low-Power Current Consumption for Deep Sleep:

- WDT: 650 nA @ 2V typical

- RTCC: 650 nA @ 32 kHz, 2V typical

- Deep Sleep current, 60 nA typical

• 160

A/MHz

in Run mode

Dual Partition Flash with Live Update

Capability

• Capable of Holding Two Independent Software Applications,

including Bootloader

• Permits Simultaneous Programming of One Partition while

Executing Application Code from the Other

• Allows Run-Time Switching Between Active Partitions

Universal Serial Bus Features

(PIC24FJXXXGB4XX Only)

• USB v2.0 On-The-Go (OTG) Compliant

• Dual Role Capable – Can Act as Either Host or Peripheral

• Low-Speed (1.5 Mb/s) and Full-Speed (12 Mb/s) USB

Operation in Host mode

• Full-Speed USB Operation in Device mode

• High-Precision PLL for USB

• USB Device mode Operation from FRC Oscillator – No Crystal

Oscillator Required

• Supports up to 32 Endpoints (16 bidirectional):

- USB module can use any RAM locations on the device as

USB endpoint buffers

• On-Chip USB Transceiver with Interface for Off-Chip

USB Transceiver

• Supports Control, Interrupt, Isochronous and Bulk Transfers

• On-Chip Pull-up and Pull-Down Resistors

High-Performance CPU

• Modified Harvard Architecture

• Up to 16 MIPS Operation @ 32 MHz

• 8 MHz Internal Oscillator:

- 96 MHz PLL option

- Multiple clock divide options

- Run-time self-calibration capability for maintaining better

than ±0.20% accuracy

- Fast start-up

• 17-Bit x 17-Bit Single-Cycle Hardware Fractional/Integer Multiplier

• 32-Bit by 16-Bit Hardware Divider

• 16 x 16-Bit Working Register Array

• C Compiler Optimized Instruction Set Architecture

• Two Address Generation Units for Separate Read and Write

Addressing of Data Memory

Special Microcontroller Features

•

20,000 Erase/Write Cycle Endurance, Typical

Data Retention: 20 Years Minimum

Self-Programmable under Software Control

Supply Voltage Range of 2.0V to 3.6V

Two On-Chip Voltage Regulators (1.8V and 1.2V) for

Regular and Extreme Low-Power Operation

Programmable Reference Clock Output

In-Circuit Serial Programming™ (ICSP™) and

In-Circuit Emulation (ICE) via 2 Pins

JTAG Boundary Scan Support

Fail-Safe Clock Monitor (FSCM) Operation:

- Detects clock failure and switches to on-chip,

Low-Power RC (LPRC) Oscillator

Power-on Reset (POR), Power-up Timer (PWRT)

and Oscillator Start-up Timer (OST)

Separate Brown-out Reset (BOR) and Deep Sleep

Brown-out Reset (DSBOR) Circuits

Programmable High/Low-Voltage Detect (HLVD)

Flexible Watchdog Timer (WDT) with its Own

RC Oscillator for Reliable Operation

Standard and Ultra Low-Power Watchdog Timers (ULPW) for

Reliable Operation in Standard and Deep Sleep modes

Temperature Range: -40°C to +85°C

Cryptographic Engine

• Performs NIST Standard Encryption/Decryption

Operations without CPU Intervention

• AES Cipher Support for 128, 192 and 256-Bit Keys

• DES/3DES Cipher Support, with up to Three Unique Keys

for 3DES

• Supports ECB, CBC, OFB, CTR and CFB128 modes

• Programmatically Secure OTP Array for Key Storage

• True Random Number Generation

• Battery-Backed RAM Key Storage

•

Analog Features

• 10/12-Bit, up to 24-Channel Analog-to-Digital (A/D) Converter:

- Conversion rate of 500 ksps (10-bit), 200 kbps (12-bit)

- Auto-scan and threshold compare features

- Conversion available during Sleep

• One 10-Bit Digital-to-Analog Converter (DAC):

- 1 Msps update rate

• Three Rail-to-Rail, Enhanced Analog Comparators with

Programmable Input/Output Configuration

• Charge Time Measurement Unit (CTMU):

- Used for capacitive touch sensing, up to 24 channels

- Time measurement down to 100 ps resolution



2015-2016 Microchip Technology Inc.

DS30010089D-page 1

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