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dsPIC33EP128GS702-I/2N

Description
Digital Signal Processor and Controller - DSP, DSC 16-bit DSC 70 MIPS 128KB Flash 8KB RAM
Categorysemiconductor    The embedded processor and controller    Digital signal processor and controller - DSP, DSC   
File Size4MB,481 Pages
ManufacturerMicrochip
Websitehttps://www.microchip.com
Environmental Compliance
Download Datasheet Download user manual Parametric View All

dsPIC33EP128GS702-I/2N Overview

Digital Signal Processor and Controller - DSP, DSC 16-bit DSC 70 MIPS 128KB Flash 8KB RAM

dsPIC33EP128GS702-I/2N Parametric

Parameter NameAttribute value
MakerMicrochip
Product CategoryDigital Signal Processors and Controllers - DSP, DSC
Package/boxUQFN-28
seriesdsPIC33EPxxxGS70x
EncapsulationTube
Factory packaging quantity61
unit weight251 mg
dsPIC33EPXXXGS70X/80X FAMILY
16-Bit Digital Signal Controllers for Digital Power Applications with
Interconnected High-Speed PWM, ADC, PGA and Comparators
Operating Conditions
• 3.0V to 3.6V, -40°C to +85°C, DC to 70 MIPS
• 3.0V to 3.6V, -40°C to +125°C, DC to 60 MIPS
Advanced Analog Features
• High-Speed ADC module:
- 12-bit with 4 dedicated SAR ADC cores and
one shared SAR ADC core
- Configurable resolution (up to 12-bit) for each
ADC core
- Up to 3.25 Msps conversion rate per channel
at 12-bit resolution
- 11 to 22 single-ended inputs
- Dedicated result buffer for each analog channel
- Flexible and independent ADC trigger sources
- Two digital comparators
- Two oversampling filters for increased
resolution
• Four Rail-to-Rail Comparators with Hysteresis:
- Dedicated 12-bit Digital-to-Analog Converter
(DAC) for each analog comparator
- Up to two DAC reference outputs
- Up to two external reference inputs
• Two Programmable Gain Amplifiers:
- Single-ended or independent ground reference
- Five selectable gains (4x, 8x, 16x, 32x and 64x)
- 40 MHz gain bandwidth
Flash Architecture
• Dual Partition Flash Program Memory with
Live Update:
- Supports programming while operating
- Supports partition soft swap
Core: 16-Bit dsPIC33E CPU
Code-Efficient (C and Assembly) Architecture
Two 40-Bit Wide Accumulators
Single-Cycle (MAC/MPY) with Dual Data Fetch
Single-Cycle Mixed-Sign MUL plus
Hardware Divide
• 32-Bit Multiply Support
• Four Additional Working Register Sets (reduces
context switching)
Clock Management
±0.9% Internal Oscillator
Programmable PLLs and Oscillator Clock Sources
Fail-Safe Clock Monitor (FSCM)
Independent Watchdog Timer (WDT)
Fast Wake-up and Start-up
Interconnected SMPS Peripherals
• Reduces CPU Interaction to Improve Performance
• Flexible PWM Trigger Options for
ADC Conversions
• High-Speed Comparator Truncates PWM
(15 ns typical):
- Supports Cycle-by-Cycle Current mode control
- Current Reset mode (variable frequency)
Power Management
• Low-Power Management modes (Sleep,
Idle, Doze)
• Integrated Power-on Reset and Brown-out Reset
• 0.5 mA/MHz Dynamic Current (typical)
• 20
μA
I
PD
Current (typical)
High-Speed PWM
• Eight PWM Generators (two outputs per generator)
• Individual Time Base and Duty Cycle for each PWM
• 1.04 ns PWM Resolution (frequency, duty cycle,
dead time and phase)
• Supports Center-Aligned, Redundant, Complementary
and True Independent Output modes
• Independent Fault and Current-Limit Inputs
• Output Override Control
• PWM Support for AC/DC, DC/DC, Inverters, PFC
and Lighting
Timers/Output Compare/Input Capture
• Five 16-Bit and up to Two 32-Bit Timers/Counters
• Four Output Compare (OC) modules, Configurable
as Timers/Counters
• Four Input Capture (IC) modules
2016-2017 Microchip Technology Inc.
DS70005258B-page 1
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