hundred-twenty-seven 64-Kword sectors (S29NS128N) and one
hundred twenty-seven 32Kword sectors (S29NS064N)
– Sixteen banks (S29NS128N and S29NS256N) and eight banks
(S29NS064N)
Program Suspend/Resume
– Suspends a programming operation to read data from a sector other
than the one being programmed, then resume the programming
operation
Unlock Bypass Program command
– Reduces overall programming time when issuing multiple program
command sequences
High Performance
– Typical word programming time of 40 µs
– Typical effective word programming time of 9.4 µs utilizing a
32-Word Write Buffer at V
CC
Level
– Typical effective word programming time of 6 µs utilizing a 32-Word
Write Buffer at ACC Level
Packages
– 48-ball Very Thin FBGA (S29NS256N)
– 44-ball Very Thin FBGA (S29NS128N, S29NS064N)
Publication Number
S29NS-N_00
Revision
A
Amendment
12
Issue Date
June 13, 2006
This document contains information on one or more products under development at Spansion LLC. The information is intended to help you evaluate this product. Do not design
in this product without contacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed product without notice.
Da ta
Sheet
( Ad vanc e
I nfo r m at io n)
1.
General Description
The S29NS256N, S29NS128N and S29NS064N are 256 Mb, 128 Mb and 64Mb (respectively), 1.8 Volt-only,
Simultaneous Read/Write, Burst Mode Flash memory devices, organized as 16,777,216, 8,388,608, and
4,194,304 words of 16 bits each. These devices use a single V
CC
of 1.70 to 1.95 V to read, program, and
erase the memory array. A 9.0-volt ACC, may be used for faster program performance if desired. These
devices can also be programmed in standard EPROM programmers.
The devices are offered at the following speeds:
Clock Speed
80 MHz
66 MHz
Burst Access (ns)
9
11.0
Synch. Initial Access (ns)
80
80
Asynch. Initial Access (ns)
80
30 pF
80
Output Loading
The devices operate within the temperature range of –25°C to
+85°C, and are offered in Very Thin FBGA packages.
1.1
Simultaneous Read/Write Operations with Zero Latency
The Simultaneous Read/Write architecture provides
simultaneous operation
by dividing the memory space
into sixteen banks. The device allows a host system to program or erase in one bank, then immediately and
simultaneously read from another bank, with zero latency. This releases the system from waiting for the
completion of program or erase operations. The devices are structured as shown in the following tables:
S29NS256N
Bank 0-14 Sectors
Quantity
240
240 Mb total
Size
64 Kwords
15
16 Mb total
64 Kwords
Quantity
4
Bank 15 Sectors
Size
16 Kwords
S29NS128N
Bank 0-14 Sectors
Quantity
120
120 Mb total
Size
64 Kwords
7
8 Mb total
64 Kwords
Quantity
4
Bank 15 Sectors
Size
16 Kwords
S29NS064N
Bank 0-6 Sectors
Quantity
112
56 Mbits
Size
32 Kwords
15
8 Mbits
32 Kwords
Quantity
4
Bank 7 Sectors
Size
8 Kwords
The VersatileIO™ (V
IO
) control allows the host system to set the voltage levels that the device generates at
its data outputs and the voltages tolerated at its data inputs to the same voltage level that is asserted on the
V
CCQ
pin.
The devices use Chip Enable (CE#), Write Enable (WE#), Address Valid (AVD#) and Output Enable (OE#) to
control asynchronous read and write operations. For burst operations, the devices additionally require Ready
(RDY) and Clock (CLK). This implementation allows easy interface with minimal glue logic to
microprocessors/microcontrollers for high performance read operations.
The devices offer complete compatibility with the
JEDEC 42.4 single-power-supply Flash command set
standard.
Commands are written to the command register using standard microprocessor write timings.
Reading data out of the device are similar to reading from other Flash or EPROM devices.
2
S29NS-N MirrorBit™ Flash Family
S29NS-N_00_A12 June 13, 2006
Data
She et
(Adva nce
In for ma ti on)
The host system can detect whether a program or erase operation is complete by using the device
status bit
DQ7 (Data# Polling) and DQ6/DQ2 (toggle bits). After a program or erase cycle has been completed, the
device automatically returns to reading array data.
The
sector erase architecture
allows memory sectors to be erased and reprogrammed without affecting the
data contents of other sectors. The devices are fully erased when shipped from the factory.
Hardware data protection
measures include a low V
CC
detector that automatically inhibits write operations
during power transitions. The devices also offer three types of data protection at the sector level.
Persistent
Sector Protection
provides in-system, command-enabled protection of any combination of sectors using a
single power supply at V
CC
.
Password Sector Protection
prevents unauthorized write and erase operations
in any combination of sectors through a user-defined 64-bit password. When at V
IL
,
WP#
locks the highest
two sectors. Finally, when ACC is at V
IL
, all sectors are locked.
The devices offer two power-saving features. When addresses have been stable for a specified amount of
time, the device enters the
automatic sleep mode.
The system can also place the device into the
standby
mode.
Power consumption is greatly reduced in both modes.
Device programming occurs by executing the program command sequence. This initiates the
Embedded
Program
algorithm - an internal algorithm that automatically times the program pulse widths and verifies
proper cell margin. The
Unlock Bypass
mode facilitates faster program times by requiring only two write
cycles to program data instead of four. Additionally,
Write Buffer Programming
is available on this family of
devices. This feature provides superior programming performance by grouping locations being programmed.
Device erasure occurs by executing the erase command sequence. This initiates the
Embedded Erase
algorithm - an internal algorithm that automatically preprograms the array (if it is not already fully
programmed) before executing the erase operation. During erase, the device automatically times the erase
pulse widths and verifies proper cell margin.
The
Program Suspend/Program Resume
feature enables the user to put program on hold to read data from
any sector that is not selected for programming. If a read is needed from the Persistent Protection area,
Dynamic Protection area, or the CFI area, after an program suspend, then the user must use the proper
command sequence to enter and exit this region. The program suspend/resume functionality is also available
when programming in erase suspend (1 level depth only).
The
Erase Suspend/Erase Resume
feature enables the user to put erase on hold to read data from, or
program data to, any sector that is not selected for erasure. True background erase can thus be achieved. If
a read is needed from the Persistent Protection area, Dynamic Protection area, or the CFI area, after an
erase suspend, then the user must use the proper command sequence to enter and exit this region.
The
hardware RESET# pin
terminates any operation in progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor to read boot-up firmware from the Flash memory
device.
The host system can detect whether a memory array program or erase operation is complete by using the
device status bit DQ7 (Data# Polling), DQ6/DQ2 (toggle bits), DQ5 (exceeded timing limit), DQ3 (sector erase
start timeout state indicator), and DQ1 (write to buffer abort). After a program or erase cycle has been
completed, the device automatically returns to reading array data.
The
sector erase architecture
allows memory sectors to be erased and reprogrammed without affecting the
data contents of other sectors.
The device is fully erased when shipped from the factory.
Hardware data protection
measures include a low V
CC
detector that automatically inhibits write operations
during power transitions. The device also offers two types of data protection at the sector level. When at V
IL
,
WP#
locks the two outermost boot sectors at the top of memory.
When the ACC pin = V
IL
, the entire flash memory array is protected.
Spansion LLC Flash technology combines years of Flash memory manufacturing experience to produce the
highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a
sector. The data is programmed using hot electron injection.
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