74HC40103
8-bit synchronous binary down counter
Rev. 5 — 21 April 2016
Product data sheet
1. General description
The 74HC40103 is an 8-bit synchronous down counter. It has control inputs for enabling
or disabling the clock (CP), for clearing the counter to its maximum count and for
presetting the counter either synchronously or asynchronously. In normal operation, the
counter is decremented by one count on each positive-going transition of the clock (CP).
Counting is inhibited when the terminal enable input (TE) is HIGH. The terminal count
output (TC) goes LOW when the count reaches zero if TE is LOW, and remains LOW for
one full clock period. When the synchronous preset enable input (PE) is LOW, data at the
jam input (P0 to P7) is clocked into the counter on the next positive-going clock transition
regardless of the state of TE. When the asynchronous preset enable input (PL) is LOW,
data at the jam input (P0 to P7) is asynchronously forced into the counter regardless of
the state of PE, TE, or CP. The jam inputs (P0 to P7) represent a single 8-bit binary word.
When the master reset input (MR) is LOW, the counter is asynchronously cleared to its
maximum count (decimal 255) regardless of the state of any other input. If all control
inputs except TE are HIGH at the time of zero count, the counters will jump to the
maximum count, giving a counting sequence of 256 clock pulses long. Device may be
cascaded using the TE input and the TC output, in either a synchronous or ripple mode.
Inputs include clamp diodes. This enables the use of current limiting resistors to interface
inputs to voltages in excess of V
CC
.
2. Features and benefits
Cascadable
Synchronous or asynchronous preset
Low-power dissipation
Complies with JEDEC standard no. 7A
CMOS input levels
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from
40 C
to +80
C
and from
40 C
to +125
C
3. Applications
Divide-by-n counters
Programmable timers
Interrupt timers
Cycle/program counters.
Nexperia
74HC40103
8-bit synchronous binary down counter
4. Ordering information
Table 1.
Ordering information
Package
Temperature range
74HC40103D
74HC40103PW
40 C
to +125
C
40 C
to +125
C
Name
SO16
TSSOP16
Description
plastic small outline package; 16 leads; body
width 3.9 mm
Version
SOT109-1
Type number
plastic thin shrink small outline package; 16 leads; SOT403-1
body width 4.4 mm
5. Functional diagram
Fig 1.
Functional diagram
Fig 2.
Logic symbol
74HC40103
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 5 — 21 April 2016
2 of 23
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Product data sheet
Rev. 5 — 21 April 2016
4 of 23
74HC40103
All information provided in this document is subject to legal disclaimers.
Nexperia
8-bit synchronous binary down counter
Fig 5.
Logic diagram
74HC40103
Nexperia
74HC40103
8-bit synchronous binary down counter
6. Pinning information
6.1 Pinning
Fig 6.
Pin configuration
6.2 Pin description
Table 2.
Symbol
CP
MR
TE
P0
P1
P2
P3
GND
PL
P4
P5
P5
P7
TC
PE
V
CC
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Description
clock input (LOW-to-HIGH, edge-triggered)
asynchronous master reset input (active LOW)
terminal enable input (active LOW)
jam input 0
jam input 1
jam input 2
jam input 3
ground (0 V)
asynchronous preset enable input (active LOW)
jam input 4
jam input 5
jam input 6
jam input 7
terminal count output (active LOW)
synchronous preset enable input (active LOW)
positive supply voltage
74HC40103
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 5 — 21 April 2016
5 of 23
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