Low Phase Noise, 1-to-8, 3.3V, 2.5V
LVPECL Output Fanout Buffer
8SLVP1208
DATA SHEET
General Description
The 8SLVP1208 is a high-performance differential LVPECL fanout
buffer. The device is designed for the fanout of high-frequency, very
low additive phase-noise clock and data signals. The 8SLVP1208 is
characterized to operate from a 3.3V and 2.5V power supply.
Guaranteed output-to-output and part-to-part skew characteristics
make the 8SLVP1208 ideal for those clock distribution applications
demanding well-defined performance and repeatability. Two
selectable differential inputs and eight low skew outputs are available.
The integrated bias voltage generators enables easy interfacing of
single-ended signals to the device inputs. The device is optimized for
low power consumption and low additive phase noise.
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
Eight low skew, low additive jitter LVPECL output pairs
Two selectable, differential clock input pairs
Differential pairs can accept the following differential input
levels: LVDS, LVPECL, CML
Maximum input clock frequency: 2GHz
LVCMOS interface levels for the control input (input select)
Output skew: 28ps (typical)
Propagation delay: 410ps (maximum)
Low additive phase jitter, RMS: 54.1fs (maximum)
(f
REF
= 156.25MHz, V
PP
= 1V, 12kHz - 20MHz)
Full 3.3V and 2.5V supply voltage
Maximum device current consumption (I
EE
): 141mA
Available in lead-free (RoHS 6), 28-Lead VFQFN package
-40°C to 85°C ambient operating temperature
Differential PCLK0, nPCLK0 and PCLK1, nPCLK1 pairs can also
accept single-ended LVCMOS levels. See Applications section
Wiring the Differential Input to Accept Single-Ended Levels
(Figure
1A
and
Figure 1B)
Block Diagram
V
CC
Pulldown
Pullup/Pulldown
Pin Assignment
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
PCLK0
nPCLK0
0
V
CC
Pulldown
Pullup/Pulldown
1
f
REF
PCLK1
nPCLK1
SEL
V
REF
Pulldown
Voltage
Reference
Q6
nQ6
Q7
nQ7
8SLVP1208
28-Lead LFCSP
5mm x 5mm x 0.75mm package body
NB Package
Top View
8SLVP1208 REVISION 1 08/28/14
1
©2014 Integrated Device Technology, Inc.
8SLVP1208 DATA SHEET
Pin Descriptions and Characteristics
Table 1. Pin Descriptions
1
Number
1, 14
2, 3
4
5
6
7
8, 15, 28
9
10
11
12, 13
16, 17
18, 19
20, 21
22, 23
24, 25
26, 27
Name
V
EE
Q7, nQ7
SEL
PCLK1
nPCLK1
V
REF
V
CC
PCLK0
nPCLK0
nc
Q0, nQ0
Q1, nQ1
Q2, nQ2
Q3, nQ3
Q4, nQ4
Q5, nQ5
Q6, nQ6
Power
Output
Input
Input
Input
Output
Power
Input
Input
Unused
Output
Output
Output
Output
Output
Output
Output
Pulldown
Pullup/
Pulldown
Pulldown
Pulldown
Pullup/
Pulldown
Type
Description
Negative supply pins.
Differential output pair. 7 LVPECL interface levels.
Reference select control. See Table 3 for function. LVCMOS/LVTTL
interface levels.
Non-inverting differential LVPECL clock/data input.
Inverting differential LVPECL clock/data input. V
CC
/2 default when left
floating.
Bias voltage reference for the nPCLK inputs.
Power supply pins.
Non-inverting differential LVPECL clock/data input.
Inverting differential LVPECL clock/data input. V
CC
/2 default when left
floating.
Do not connect.
Differential output pair 0. LVPECL interface levels.
Differential output pair 1. LVPECL interface levels.
Differential output pair 2. LVPECL interface levels.
Differential output pair 3. LVPECL interface levels.
Differential output pair 4. LVPECL interface levels.
Differential output pair 5. LVPECL interface levels.
Differential output pair 6. LVPECL interface levels.
NOTE 1:
Pulldown
and
Pullup
refer to internal input resistors. See
Table 2, Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLDOWN
R
PULLUP
Parameter
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
Test Conditions
Minimum
Typical
2
51
51
Maximum
Units
pF
k
k
Function Table
Table 3. SEL Input Selection Function Table
1
Input
SEL
0 (default)
1
Operation
PCLK0, nPCLK0 is the selected differential clock input
PCLK1, nPCLK1 is the selected differential clock input
NOTE 1: SEL is an asynchronous control.
LOW PHASE NOISE, 1-TO-8, 3.3V, 2.5V LVPECL OUTPUT
FANOUT BUFFER
2
REVISION 1 08/28/14
8SLVP1208 DATA SHEET
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the
DC Electrical Characteristics
or
AC Electrical Characteristics
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Item
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
(LVPECL)
Continuous Current
Surge Current
Input Sink/Source, IREF
Maximum Junction Temperature, T
J,MAX
Storage Temperature, T
STG
ESD - Human Body Model
1
ESD - Charged Device Model
1
NOTE 1: According to JEDEC/JESD 22-A114/22-C101.
Rating
3.63V
-0.5V to V
CC
+ 0.5V
50mA
100mA
±2mA
125°C
-65C to 150C
2000V
1500V
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
CC
= 3.3V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
CC
I
EE
I
CC
Parameter
Power Supply Voltage
Power Supply Current
Power Supply Current
Q0 to Q7 terminated 50 to V
CC
– 2V
Test Conditions
Minimum
3.135
Typical
3.3V
110
285
Maximum
3.465
141
343
Units
V
mA
mA
Table 4B. Power Supply DC Characteristics,
V
CC
= 2.5V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
CC
I
EE
I
CC
Parameter
Power Supply Voltage
Power Supply Current
Power Supply Current
Q0 to Q7 terminated 50
to V
CC
– 2V
Test Conditions
Minimum
2.375
Typical
2.5V
102
285
Maximum
2.625
127
341
Units
V
mA
mA
REVISION 1 08/28/14
3
LOW PHASE NOISE, 1-TO-8, 3.3V, 2.5V LVPECL OUTPUT
FANOUT BUFFER
8SLVP1208 DATA SHEET
Table 4C. LVCMOS/LVTTL DC Characteristics,
V
CC
= 3.3V ± 5% or 2.5V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Test Conditions
V
CC
= 3.465V
V
CC
= 2.625V
V
CC
= 3.465V
V
CC
= 2.625V
V
CC
= V
IN
= 3.465V or 2.625V
V
CC
= 3.465V or 2.625V, V
IN
= 0V
-10
Minimum
2.2
1.7
-0.3
-0.3
Typical
Maximum
V
CC
+ 0.3
V
CC
+ 0.3
0.8
0.7
150
Units
V
V
V
V
µA
µA
Input Low Voltage
Input High
Current
Input Low
Current
SEL
SEL
Table 4D. LVPECL DC Characteristics,
V
CC
= 3.3V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
1
Symbol
I
IH
I
IL
V
REF
V
OH
V
OL
Parameter
Input High
Current
Input Low
Current
PCLK0, nPCLK0
PCLK1, nPCLK1
PCLK0, PCLK1
nPCLK0, nPCLK1
Test Conditions
V
CC
= V
IN
= 3.465V
V
CC
= 3.465V, V
IN
= 0V
V
CC
= 3.465V, V
IN
= 0V
I
REF
= 2mA
-10
-150
V
CC
– 1.83
V
CC
– 1.23
V
CC
– 1.97
V
CC
– 1.54
V
CC
– 1.16
V
CC
– 1.90
V
CC
– 1.25
V
CC
– 0.80
V
CC
– 1.70
Minimum
Typical
Maximum
150
Units
µA
µA
µA
V
V
V
Reference Voltage for Input
Bias
Output High Voltage
2
Output Low Voltage
2
NOTE 1: Input and output parameters vary 1:1 with V
CC
.
NOTE 2: Outputs terminated with 50 to V
CC
– 2V.
Table 4E. LVPECL DC Characteristics,
V
CC
= 2.5V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
1
Symbol
I
IH
I
IL
V
REF
V
OH
V
OL
Parameter
Input High
Current
Input Low
Current
PCLK0, nPCLK0
PCLK1, nPCLK1
PCLK0, PCLK1
Test Conditions
V
CC
= V
IN
= 2.625V
V
CC
= 2.625V, V
IN
= 0V
-10
-150
V
CC
– 1.64
V
CC
– 1.21
V
CC
– 1.92
V
CC
– 1.36
V
CC
– 1.00
V
CC
– 1.80
V
CC
– 1.09
V
CC
– 0.79
V
CC
– 1.67
Minimum
Typical
Maximum
150
Units
µA
µA
µA
V
V
V
nPCLK0, nPCLK1 V
CC
= 2.625V, V
IN
= 0V
I
REF
= 2mA
Reference Voltage for Input
Bias
Output High Voltage
2
Output Low Voltage
2
NOTE 1: Input and output parameters vary 1:1 with V
CC
.
NOTE 2: Outputs terminated with 50 to V
CC
– 2V.
LOW PHASE NOISE, 1-TO-8, 3.3V, 2.5V LVPECL OUTPUT
FANOUT BUFFER
4
REVISION 1 08/28/14
8SLVP1208 DATA SHEET
AC Electrical Characteristics
Table 5A. AC Electrical Characteristics,
V
CC
= 3.3V ± 5% or 2.5V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
1
Symbol
f
REF
V/t
t
PD
tsk(o)
tsk(i)
tsk(p)
tsk(pp)
t
R
/ t
F
MUX
ISOLATION
V
PP
V
CMR
Vo
(pp)
V
DIFF_OUT
Parameter
Input
Frequency
Input
Edge Rate
PCLK[0:1],
nPCLK[0:1]
PCLK[0:1],
nPCLK[0:1]
PCLK[0:1], nPCLK[0:1] to any Qx, nQx
for V
PP,IN
= 0.1V or 0.3V
1.5
160
287
28
12
f
REF
= 100MHz
20% to 80%
29
29
55
104
76
f < 1.5GHz
f > 1.5GHz
0.1
0.2
1.0
V
CC
= 3.3V, f
REF
2GHz
V
CC
= 2.5V, f
REF
2GHz
V
CC
= 3.3V, f
REF
2GHz
V
CC
= 2.5V, f
REF
2GHz
0.5
0.5
1.0
1.0
0.83
0.82
1.67
1.63
1.5
1.5
V
CC
– 0.6
1.10
1.05
2.20
2.10
410
64
65
70
140
200
Test Conditions
Minimum
Typical
Maximum
2
Units
GHz
V/ns
ps
ps
ps
ps
ps
ps
dB
V
V
V
V
V
V
V
Propagation Delay
2
Output Skew
3, 4
Input Skew
4
Pulse Skew
Part-to-Part Skew
4, 5
Output Rise/ Fall Time
Mux Isolation
6
Peak-to-Peak
Input Voltage
7, 8
Common Mode
Input Voltage
7, 8, 9
Output Voltage Swing,
Peak-to-Peak
Differential Output Voltage
Swing, Peak to Peak
NOTE 1: NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the
device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after
thermal equilibrium has been reached under these conditions.
NOTE 2: Measured from the differential input crossing point to the differential output crossing point.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential crosspoints.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 5: Defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 6: Qx, nQx outputs measured differentially. See
MUX Isolation
diagram in the
Parameter Measurement Information
section.
NOTE 7: V
IL
should not be less than -0.3V. V
IH
should not be higher than V
CC
.
NOTE 8: For single-ended LVCMOS input applications, please refer to the
Applications Information, Wiring the Differential Input to Accept Sin-
gle-Ended Levels, Figure 1A
and
Figure 1B.
NOTE 9: Common mode input voltage is defined as the crosspoint.
REVISION 1 08/28/14
5
LOW PHASE NOISE, 1-TO-8, 3.3V, 2.5V LVPECL OUTPUT
FANOUT BUFFER
Embedded System
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