DATASHEET
ISL70040SEH, ISL73040SEH
Radiation Hardened Low-Side GaN FET Driver
FN8984
Rev.5.00
Jul 12, 2018
The
ISL70040SEH
and
ISL73040SEH
are low-side
drivers designed to drive enhancement mode Gallium
Nitride (GaN) FETs in isolated topologies and boost type
configurations. The ISL70040SEH operates with a
supply voltage from 4.5V to 13.2V and has both
inverting (INB) and non-inverting (IN) inputs to satisfy
requirements for inverting and non-inverting gate drives
with a single device.
The ISL70040SEH and ISL73040SEH have a 4.5V gate
drive voltage (V
DRV
) generated using an internal
regulator which prevents the gate voltage from exceeding
the maximum gate-source rating of enhancement mode
GaN FETs. The gate drive voltage also features an
undervoltage lockout (UVLO) protection that ignores the
inputs (IN/INB) and keeps OUTL turned on to ensure the
GaN FET is in an OFF state whenever V
DRV
is below the
UVLO threshold.
The ISL70040SEH and ISL73040SEH inputs can
withstand voltages up to 14.7V regardless of the V
DD
voltage. This allows the ISL70040SEH and
ISL73040SEH inputs to be connected directly to most
PWM controllers. The ISL70040SEH and ISL73040SEH
split outputs offer the flexibility to adjust the turn-on and
turn-off speed independently by adding additional
impedance to the turn-on/off paths.
The ISL70040SEH and ISL73040SEH operate across
the military temperature range from -55°C to +125°C
and are offered in an 8 Ld hermetically sealed ceramic
Surface Mount Device (SMD) package or die form.
Features
• Wide operating voltage range of 4.5V to 13.2V
• Up to 14.7V logic inputs (regardless of V
DD
level)
• Inverting and non-inverting inputs
• Optimized to drive enhancement mode GaN FETs
• Internal 4.5V regulated gate drive voltage
• Independent outputs for adjustable
turn-on/turn-off speeds
• Full military temperature range operation
• T
A
= -55°C to +125°C
• T
J
= -55°C to +150°C
• Radiation hardness assurance (wafer-by-wafer)
• High Dose Rate (HDR) (50-300rad(Si)/s):
100krad(Si) (ISL70040SEH only)
• Low Dose Rate (LDR) (0.01rad(Si)/s): 75krad(Si)
• SEE hardness (refer to the
ISL70040SEH,
ISL73040SEH SEE Report
for details)
• No SEB/L LET
TH
, V
DD
= 14.7V: 86MeV•cm
2
/mg
• No SET, LET
TH
, V
DD
= 13.2V: 86MeV•cm
2
/mg
• Electrically screened to DLA SMD
5962-17233
Applications
• Flyback and forward converters
• Boost and PFC converters
• Secondary synchronous FET drivers
Related Literature
For a full list of related documents, visit our website
•
ISL70040SEH
and
ISL73040SEH
product pages
22V - 36V
12V
4.8
Gate Drive Voltage (V)
4.7
-55°C
4.6
4.5
+25°C
12V
1
VDD
IN
INB
PWM
Controller
ISL7884xSEH
IS-1825BSEH
VDRV
8
OUTH
7
OUTL
6
VSSP
5
2
3
ISL70023SEH
4.4
4.3
4.2
+125°C
100V GaN FET
4
VSS
ISL70040SEH/
ISL73040SEH
4
5
6
7
8
9
V
DD
(V)
10
11
12
13
14
Figure 1. ISL70040SEH/ISL73040SEH 8 Ld SMD Package
Figure 2. V
DRV
Line Regulation vs Temperature
FN8984 Rev.5.00
Jul 12, 2018
Page 1 of 20
ISL70040SEH, ISL73040SEH
Contents
1.
1.1
1.2
1.3
1.4
1.5
2.
2.1
2.2
2.3
2.4
2.5
3.
4.
4.1
4.2
5.
5.1
5.2
5.3
5.4
5.5
6.
6.1
6.2
7.
8.
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
3
4
5
5
Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6
6
6
7
8
Typical Performance Curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Gate Drive for N-Channel GaN FETs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Applications Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Undervoltage Lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Stage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Enable Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Dissipation of the Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General PCB Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13
13
13
14
14
Die and Assembly Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Metallization Mask Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Bond Pad Coordinates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
FN8984 Rev.5.00
Jul 12, 2018
Page 2 of 20
ISL70040SEH, ISL73040SEH
1. Overview
1.
1.1
Overview
Typical Application Schematic
R8
CR1
VIN+
L1
ISL70024SEH
C1
Q
1
R4
+
+VOUT
C10
C2
C3
R1
R2
VIN+
C4
C11
VDD
IN
INB
VSS
U1
VDRV
OUTH
OUTL
VSSP
R5
C
12
ISL70040SEH
C9
RTCT
CS
COMP
FB
ISL7884xASEH
C7
R3
R7
C8
VREF
R6
GND
VDD
OUT
U
2
VIN+
C5
C6
Figure 3. ISL70040SEH and ISL73040SEH Typical Application Schematic
1.2
Functional Block Diagram
Figure 4. Block Diagram
FN8984 Rev.5.00
Jul 12, 2018
Page 3 of 20
ISL70040SEH, ISL73040SEH
1. Overview
1.3
Ordering Information
Part Number
(Note 2)
ISL70040SEHVL
ISL70040SEHVX
ISL70040SEHL/PROTO
(Note 3)
ISL70040SEHX/SAMPLE
(Note 3)
ISL70040SEHEV2Z
(Note 4)
ISL70040SEHEV3Z
(Note 4)
ISL73040SEHVL
ISL73040SEHVX
ISL73040SEHL/PROTO
(Note 3)
ISL73040SEHX/SAMPLE
(Note 3)
Radiation Hardness
(Total Ionizing Dose)
HDR
100krad(Si)
100krad(Si)
-
-
LDR
75krad(Si)
75krad(Si)
-
-
Temperature
Range (°C)
-55 to +125
-55 to +125
-55 to +125
-55 to +125
Package
(RoHS
Compliant)
8 Ld SMD
Die
8 Ld SMD
Die
Package
Drawing
J8.A
-
J8.A
-
Ordering SMD Number
(Note 1)
5962R1723301VXC
5962R1723301V9A
N/A
N/A
N/A
N/A
5962L1723302VXC
5962L1723302V9A
N/A
N/A
Evaluation Board with ISL70040SEH/ISL70023SEH
Evaluation Board with ISL70040SEH/ISL70024SEH
-
-
-
-
75krad(Si)
75krad(Si)
-
-
-55 to +125
-55 to +125
-55 to +125
-55 to +125
8 Ld SMD
Die
8 Ld SMD
Die
J8.A
-
J8.A
-
Notes:
1. Specifications for Rad Hard QML devices are controlled by the Defense Logistics Agency Land and Maritime (DLA). The SMD
numbers listed must be used when ordering.
2. These Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and
compatible with both SnPb and Pb-free soldering operations.
3. The /PROTO and /SAMPLE are not rated or certified for Total Ionizing Dose (TID) or Single Event Effect (SEE) immunity. These
parts are intended for engineering evaluation purposes only. The /PROTO parts meet the electrical limits and conditions across
the temperature range specified in the DLA SMD and are in the same form and fit as the qualified device. The /SAMPLE die is
capable of meeting the electrical limits and conditions specified in the DLA SMD at +25°C only. The /SAMPLE is a die and does
not receive 100% screening across the temperature range to the DLA SMD electrical limits. These part types do not come with
a certificate of conformance because there is no radiation assurance testing and they are not DLA qualified devices.
4. Evaluation board uses the /PROTO parts. The /PROTO parts are not rated or certified for Total Ionizing Dose (TID) or Single
Event Effect (SEE) immunity.
Table 1. Key Differences Between Family of Parts
Part Number
ISL70040SEH
ISL73040SEH
HDR to 100krad(Si)
LDR to 75krad(Si)
LDR to 75krad(Si)
Differences Between Parts
FN8984 Rev.5.00
Jul 12, 2018
Page 4 of 20
ISL70040SEH, ISL73040SEH
1. Overview
1.4
Pin Configuration
8 Ld SMD
VDD
IN
INB
VSS
1
2
3
4
8 VDRV
7 OUTH
6 OUTL
5 VSSP
NOTE: The ESD triangular mark indicates Pin #1. It is a part of the device
marking and is placed on the lid in the quadrant where Pin #1 is located.
Branding
Name Area
1.5
1
2
Pin Descriptions
Pin Name ESD Circuit
VDD
IN
3
3
Description
Supply for the ISL70040SEH and ISL73040SEH internal linear regulator. Locally bypass
the supply to VDD using at least a 4.7µF ceramic capacitor.
Non-inverting input pin which controls the OUTH and OUTL outputs. This input has
TTL/CMOS type thresholds. When using this device in an inverting application, tie this pin
to VDD to enable the outputs.
Inverting input pin which controls the OUTH and OUTL outputs. This input has TTL/CMOS
type thresholds. When using this device in a non-inverting application, tie this pin to VSS to
enable the outputs.
Supply ground. Connect this pin to VSSP from the PCB ground plane.
Power supply ground. Connect this pin to VSS from the PCB ground plane.
Output low pin which is the gate driver turn-off output. Connect to the gate of the GaN FET
with a short, low inductance path. A series gate resistor can be used to adjust the turn-off
speed.
Output high pin which is the gate driver turn-on output. Connect to the gate of the GaN FET
with a short, low inductance path. A series gate resistor can be used to adjust the turn-on
speed.
Internal linear regulator output and the gate drive voltage. Locally bypass this pin using at
least a 4.7µF ceramic capacitor; 2µF to 10µF with variability.
Internally connected to VSSP (Pin 5).
VDRV
7V
PIN #
7V
7V
VSS
VSSP
Circuit 2
17V
VSS
VS
17V
VSSP
Circuit 4
VSSP
Pin Number
3
INB
3
4
5
6
VSS
VSSP
OUTL
4
4
2
7
OUTH
1
8
N/A
VDRV
LID
1
N/A
PIN #
7V
VS
7V
VSS
Circuit 1
PIN #
VSS
Circuit 3
FN8984 Rev.5.00
Jul 12, 2018
Page 5 of 20
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