GS82582QT38GE-450 datasheet, PDF

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GS82582QT38GE-450: DescriptionStatic random access memory 1.5/1.8V 8M x 36 288M; Categorysemiconductor Memory IC Static random access memory; File Size305KB，25 Pages; ManufacturerGSI Technology; Websitehttp://www.gsitechnology.com/; Environmental Compliance

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GS82582QT38GE-450 Overview

Static random access memory 1.5/1.8V 8M x 36 288M

GS82582QT38GE-450 Parametric

Parameter Name	Attribute value
Maker	GSI Technology
Product Category	static random access memory
storage	288 Mbit
organize	8 M x 36
maximum clock frequency	450 MHz
Interface Type	Parallel
Supply voltage - max.	1.9 V
Supply voltage - min.	1.7 V
Supply current—max.	1.46 A
Minimum operating temperature	0 C
Maximum operating temperature	+ 70 C
Installation style	SMD/SMT
Package/box	BGA-165
Encapsulation	Tray
storage type	QDR-II
series	GS82582QT38GE
type	SigmaQuad-II+ B2
Factory packaging quantity	10

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GS82582QT20/38GE-500/450/400/375

165-Bump BGA

Commercial Temp

Industrial Temp

Features

• 2.5 clock Latency

• Simultaneous Read and Write SigmaQuad™ Interface

• JEDEC-standard pinout and package

• Dual Double Data Rate interface

• Byte Write controls sampled at data-in time

• Dual-Range On-Die Termination (ODT) on Data (D), Byte

Write (BW), and Clock (K, K) inputs

• Burst of 2 Read and Write

• 1.8 V +100/–100 mV core power supply

• 1.5 V or 1.8 V HSTL Interface

• Pipelined read operation

• Fully coherent read and write pipelines

• ZQ pin for programmable output drive strength

• Data Valid Pin (QVLD) Support

• IEEE 1149.1 JTAG-compliant Boundary Scan

• RoHS-compliant 165-bump BGA package

288Mb SigmaQuad-II+

Burst of 2 SRAM

500 MHz–375 MHz

1.8 V V

1.8 V and 1.5 V I/O

just one element in a family of low power, low voltage HSTL

I/O SRAMs designed to operate at the speeds needed to

implement economical high performance networking systems.

Clocking and Addressing Schemes

The GS82582QT20/38GE SigmaQuad-II+ SRAMs are

synchronous devices. They employ two input register clock

inputs, K and K. K and K are independent single-ended clock

inputs, not differential inputs to a single differential clock input

buffer.

Each internal read and write operation in a SigmaQuad-II+ B2

RAM is two times wider than the device I/O bus. An input data

bus de-multiplexer is used to accumulate incoming data before

it is simultaneously written to the memory array. An output

data multiplexer is used to capture the data produced from a

single memory array read and then route it to the appropriate

output drivers as needed. Therefore the address field of a

SigmaQuad-II+ B2 RAM is always one address pin less than

the advertised index depth (e.g., the 16M x 18 has an 8M

addressable index).

SigmaQuad™ Family Overview

The GS82582QT20/38GE are built in compliance with the

SigmaQuad-II+ SRAM pinout standard for Separate I/O

synchronous SRAMs. They are 301,989,888-bit (288Mb)

SRAMs. The GS82582QT20/38GE SigmaQuad SRAMs are

Parameter Synopsis

-500

tKHKH

tKHQV

2.0 ns

0.45 ns

-450

2.2 ns

0.45 ns

-400

2.5 ns

0.45 ns

-375

2.66 ns

0.45 ns

Rev: 1.04 11/2017

1/25

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS82582QT20/38GE-500/450/400/375

Background

Separate I/O SRAMs, from a system architecture point of view, are attractive in applications where alternating reads and writes are

needed. Therefore, the SigmaQuad-II+ SRAM interface and truth table are optimized for alternating reads and writes. Separate I/O

SRAMs are unpopular in applications where multiple reads or multiple writes are needed because burst read or write transfers from

Separate I/O SRAMs can cut the RAM’s bandwidth in half.

SigmaQuad-II B2 SRAM DDR Read

The read port samples the status of the Address Input and R pins at each rising edge of K. A low on the Read Enable-bar pin, R,

begins a read cycle. Clocking in a high on the Read Enable-bar pin, R, begins a read port deselect cycle.

SigmaQuad-II B2 SRAM DDR Write

The write port samples the status of the W pin at each rising edge of K and the Address Input pins on the following rising edge of

K. A low on the Write Enable-bar pin, W, begins a write cycle. The first of the data-in pairs associated with the write command is

clocked in with the same rising edge of K used to capture the write command. The second of the two data in transfers is captured on

the rising edge of K along with the write address. Clocking in a high on W causes a write port deselect cycle.

Special Functions

Byte Write Control

Byte Write Enable pins are sampled at the same time that Data In is sampled. A High on the Byte Write Enable pin associated with

a particular byte (e.g., BW0 controls D0–D8 inputs) will inhibit the storage of that particular byte, leaving whatever data may be

stored at the current address at that byte location undisturbed. Any or all of the Byte Write Enable pins may be driven High or Low

during the data in sample times in a write sequence.

Each write enable command and write address loaded into the RAM provides the base address for a 2beat data transfer. The x18

version of the RAM, for example, may write 36 bits in association with each address loaded. Any 9-bit byte may be masked in any

write sequence.

Example x18 RAM Write Sequence using Byte Write Enables

Data In Sample Time

Beat 1

Beat 2

BW0

BW1

D0–D8

Data In

Don’t Care

D9–D17

Don’t Care

Data In

Resulting Write Operation

Byte 1

D0–D8

Written

Beat 1

Byte 2

D9–D17

Unchanged

Byte 3

D0–D8

Unchanged

Beat 2

Byte 4

D9–D17

Written

Rev: 1.04 11/2017

5/25

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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