Low Skew, 2:1 LVDS MUX with 1:8
Fanout and Internal Termination
Data Sheet
8S89200
General Description
The 8S89200 is a high speed 1-to-8 Differential-to-LVDS Clock
Divider and is part of the high performance clock solutions from IDT.
The 8S89200 is optimized for high speed and very low output skew,
making it suitable for use in demanding applications such as SONET,
1 Gigabit and 10 Gigabit Ethernet, and Fibre Channel. The internally
terminated differential inputs and V
REF_AC
pins allow other
differential signal families such as LVPECL, LVDS and CML to be
easily interfaced to the input with minimal use of external
components.
The device also has a selectable ÷1, ÷2, ÷4 output divider, which can
allow the part to support multiple output frequencies from the same
reference clock.
The 8S89200 is packaged in a small 5mm x 5mm 32-pin VFQFN
package which makes it ideal for use in space-constrained
applications.
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
Three output banks, consisting of eight LVDS output pairs total
INx, nINx inputs can accept the following differential input levels:
LVPECL, LVDS, CML
Selectable output divider values of ÷1, ÷2 and ÷4
Maximum output frequency: 1.5GHz
Maximum input frequency: 3GHz
Bank Skew: 10ps (typical)
Part-to-part skew: 100ps (typical)
Additive phase jitter, RMS: 0.170ps (typical)
Propagation delay: 802ps (typical)
Output rise time: 150ps (typical)
2.5V±5% operating supply voltage
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Pin Assignment
nQA0
nQA1
nQA2
nMR
QA0
QA1
QA2
V
DD
32 31 30
GND
DIVSEL_A
IN
V
T
V
REF_AC
nIN
DIVSEL_B
DIVSEL_C
1
2
3
4
5
6
7
8
9
EN
29 28
27 26 25
24
23
22
QA3
nQA3
V
DD
GND
GND
V
DD
QC
nQC
8S89200
21
20
19
18
17
10 11 12 13 14 15 16
nQB2
nQB1
QB2
QB1
nQB0
QB0
V
DD
32-Lead 5mm x 5mm VFQFN
©2016 Integrated Device Technology, Inc
1
Revision B February 8, 2016
Block Diagram
D IV SE L_A
P ullup
QA0
nQ A 0
÷1
÷1
QA1
nQ A 1
IN
R
IN
=50
QA2
÷2
÷2
nQ A 2
V
T
R
IN
=50
nIN
QA3
÷4
EN
nM R
P ullup
P ullup
nQ A 3
QB0
nQ B 0
V
R E F _A C
÷2
QB1
nQ B 1
÷4
QB2
P ullup
nQ B 2
D IV SE L_B
÷2
QC
nQ C
÷4
D IV SE L _C
P ullup
8S89200 Data Sheet
Table 1. Pin Descriptions
Number
1, 20, 21
2
3
4
5
6
7
8
9
10, 19, 22, 31
11, 12
13, 14
15, 16
17, 18
23, 24
25, 26
27, 28
29, 30
32
Name
GND
DIVSEL_A
IN
V
T
V
REF_AC
nIN
DIVSEL_B
DIVSEL_C
EN
V
DD
nQB2, QB2
nQB1, QB1
nQB0, QB0
nQC, QC
nQA3, QA3
nQA2, QA2
nQA1, QA1
nQA0, QA0
nMR
Power
Input
Input
Input
Output
Input
Input
Input
Input
Power
Output
Output
Output
Output
Output
Output
Output
Output
Input
Pullup
Pullup
Pullup
Pullup
Pullup
Type
Description
Ground supply pins.
Output divider select pin. Controls output divider settings for Bank A.
See Table 3 for additional information. LVCMOS/LVTTL interface levels.
Non-inverting differential LVPECL clock input. R
IN
= 50
termination to V
T.
Termination center-tap input.
Reference voltage for AC-coupled applications.
Inverting differential LVPECL clock input. R
IN
= 50
termination to V
T.
Output divider select pin. Controls output divider settings for Bank B.
See Table 3 for additional information. LVCMOS/LVTTL interface levels.
Output divider select pin. Controls output divider settings for Bank C.
See Table 3 for additional information. LVCMOS/LVTTL interface levels.
Output enable pin. See Table 3 for additional information.
LVCMOS/LVTTL interface levels.
Positive supply pins.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Master Reset. See Table 3 for additional information.
LVCMOS/LVTTL interface levels.
NOTE:
Pullup
refers to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
Parameter
Input Capacitance
Input Pullup Resistor
Test Conditions
Minimum
Typical
2
25
Maximum
Units
pF
k
©2016 Integrated Device Technology, Inc
3
Revision B February 8, 2016
8S89200 Data Sheet
Function Tables
Table 3. SEL Function Table
nMR
0
1
1
1
EN
n/a
0
1
1
DIVSEL_A
n/a
n/a
0
1
DIVSEL_B
n/a
n/a
0
1
DIVSEL_C
n/a
n/a
0
1
Output Bank A
0
0
÷1
÷2
Output Bank B
0
0
÷2
÷4
Output Bank C
0
0
÷2
÷4
Figure 1A. Reset with Output Enabled
©2016 Integrated Device Technology, Inc
4
Revision B February 8, 2016
8S89200 Data Sheet
1
nIN
IN
2
3
4
EN
V
DD
/2
Enabled asserted
nQ
÷1 Output
Q
nQ
÷2 Output
Q
nQ
÷4 Output
Q
Outputs go HIGH simultaneously after EN is asserted.
The number of IN clock cycles after EN is asserted before
the outputs go HIGH varies from 2 to 6 cycles (4 cycles shown).
Figure 1B. Enabled Timing
©2016 Integrated Device Technology, Inc
5
Revision B February 8, 2016
京公网安备 11010802033920号
EEWORLD
