DisplayPort Intel
®
FPGA IP User
Guide
Updated for Intel
®
Quartus
®
Prime Design Suite:
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UG-01131 | 2018.05.07
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Contents
Contents
1. DisplayPort Intel
®
FPGA IP Quick Reference...................................................................9
1.1. DisplayPort Terms and Acronyms........................................................................... 10
2. About This IP Core........................................................................................................ 12
2.1. Device Family Support.......................................................................................... 13
2.2. IP Core Verification.............................................................................................. 14
2.3. Performance and Resource Utilization..................................................................... 14
3. Getting Started............................................................................................................. 16
3.1. Installing and Licensing Intel FPGA IP Cores............................................................ 16
3.1.1. Intel FPGA IP Evaluation Mode................................................................... 17
3.2. Specifying IP Core Parameters and Options............................................................. 19
3.3. Simulating the Design.......................................................................................... 19
3.3.1. Simulating with the ModelSim Simulator..................................................... 20
3.4. Compiling the Full Design and Programming the FPGA.............................................. 20
4. DisplayPort Intel FPGA IP Core Hardware Design Examples......................................... 21
4.1. DisplayPort Intel FPGA IP Hardware Design Examples for Intel Arria 10 and Intel
Cyclone 10 GX Devices...................................................................................... 21
4.2. DisplayPort Intel FPGA IP Hardware Design Examples for Arria V, Cyclone V, and
Stratix V Devices...............................................................................................21
4.2.1. Clock Recovery Core.................................................................................25
4.2.2. Transceiver and Clocking...........................................................................30
4.2.3. Required Hardware...................................................................................32
4.2.4. Design Walkthrough................................................................................. 32
4.2.5. DisplayPort Link Training Flow....................................................................38
4.2.6. DisplayPort Post Link Training Adjust Request Flow (LQA).............................. 39
4.2.7. DisplayPort MST Source User Application.....................................................40
5. DisplayPort Source....................................................................................................... 42
5.1. Main Data Path.................................................................................................... 43
5.1.1. Video Packetizer Path............................................................................... 43
5.1.2. Video Geometry Measurement Path............................................................ 44
5.1.3. Audio and Secondary Stream Encoder Path..................................................44
5.1.4. Training and Link Quality Patterns Generator............................................... 45
5.2. Controller Interface.............................................................................................. 45
5.3. Sideband Channel................................................................................................ 45
5.4. Source Embedded DisplayPort (eDP) Support...........................................................46
5.5. Source Interfaces................................................................................................ 46
5.5.1. Controller Interface.................................................................................. 50
5.5.2. AUX Interface..........................................................................................51
5.5.3. Video Interface........................................................................................ 51
5.5.4. TX Transceiver Interface........................................................................... 55
5.5.5. Transceiver Reconfiguration Interface......................................................... 55
5.5.6. Transceiver Analog Reconfiguration Interface............................................... 56
5.5.7. Secondary Stream Interface...................................................................... 56
5.5.8. Audio Interface........................................................................................59
5.6. Source Clock Tree................................................................................................ 63
DisplayPort Intel
®
FPGA IP User Guide
2
Contents
6. DisplayPort Sink........................................................................................................... 65
6.1. Sink Embedded DisplayPort (eDP) Support.............................................................. 67
6.2. Sink Interfaces.................................................................................................... 67
6.2.1. Controller Interface.................................................................................. 72
6.2.2. AUX Interface..........................................................................................72
6.2.3. Debugging Interface.................................................................................73
6.2.4. Video Interface........................................................................................ 74
6.2.5. Clocked Video Input Interface....................................................................76
6.2.6. RX Transceiver Interface........................................................................... 77
6.2.7. Transceiver Reconfiguration Interface......................................................... 78
6.2.8. Secondary Stream Interface...................................................................... 78
6.2.9. Audio Interface........................................................................................80
6.2.10. MSA Interface........................................................................................81
6.3. Sink Clock Tree....................................................................................................83
7. DisplayPort Intel FPGA IP Parameters.......................................................................... 85
7.1. DisplayPort Intel FPGA IP Source Parameters........................................................... 85
7.2. DisplayPort Intel FPGA IP Sink Parameters ............................................................. 86
8. DisplayPort Intel FPGA IP Core Simulation Example..................................................... 88
8.1. Design Walkthrough............................................................................................. 88
8.1.1. Copy the Simulation Files to Your Working Directory..................................... 89
8.1.2. Generate the IP Simulation Files and Scripts, and Compile and Simulate......... 90
8.1.3. View the Results...................................................................................... 91
9. DisplayPort API Reference............................................................................................ 94
9.1. Using the Library................................................................................................. 94
9.2. btc_dprx_syslib API Reference............................................................................... 96
9.3. btc_dprx_aux_get_request....................................................................................96
9.4. btc_dprx_aux_handler..........................................................................................97
9.5. btc_dprx_aux_post_reply......................................................................................98
9.6. btc_dprx_baseaddr.............................................................................................. 98
9.7. btc_dprx_dpcd_gpu_access...................................................................................98
9.8. btc_dprx_edid_set............................................................................................... 99
9.9. btc_dprx_hpd_get................................................................................................99
9.10. btc_dprx_hpd_pulse......................................................................................... 100
9.11. btc_dprx_hpd_set............................................................................................ 100
9.12. btc_dprx_lt_eyeq_init....................................................................................... 101
9.13. btc_dprx_lt_force............................................................................................. 101
9.14. btc_dprx_rtl_ver.............................................................................................. 102
9.15. btc_dprx_sw_ver..............................................................................................102
9.16. btc_dprx_syslib_add_rx.................................................................................... 102
9.17. btc_dprx_syslib_info......................................................................................... 103
9.18. btc_dprx_syslib_init..........................................................................................103
9.19. btc_dprx_syslib_monitor................................................................................... 104
9.20. btc_dptx_syslib API Reference........................................................................... 104
9.21. btc_dptx_aux_i2c_read..................................................................................... 104
9.22. btc_dptx_aux_i2c_write.................................................................................... 105
9.23. btc_dptx_aux_read...........................................................................................106
9.24. btc_dptx_aux_write.......................................................................................... 106
9.25. btc_dptx_baseaddr........................................................................................... 107
DisplayPort Intel
®
FPGA IP User Guide
3
Contents
9.26.
9.27.
9.28.
9.29.
9.30.
9.31.
9.32.
9.33.
9.34.
9.35.
9.36.
9.37.
9.38.
9.39.
9.40.
9.41.
9.42.
9.43.
9.44.
9.45.
9.46.
9.47.
9.48.
9.49.
9.50.
9.51.
9.52.
9.53.
9.54.
9.55.
9.56.
9.57.
9.58.
9.59.
9.60.
9.61.
9.62.
9.63.
9.64.
9.65.
9.66.
9.67.
9.68.
9.69.
9.70.
9.71.
9.72.
9.73.
9.74.
9.75.
9.76.
btc_dptx_edid_block_read................................................................................. 107
btc_dptx_edid_read..........................................................................................108
btc_dptx_fast_link_training............................................................................... 108
btc_dptx_hpd_change.......................................................................................109
btc_dptx_is_link_up..........................................................................................109
btc_dptx_link_bw............................................................................................. 109
btc_dptx_link_training...................................................................................... 110
btc_dptx_rtl_ver.............................................................................................. 110
btc_dptx_set_color_space................................................................................. 110
btc_dptx_sw_ver..............................................................................................111
btc_dptx_syslib_add_tx.....................................................................................111
btc_dptx_syslib_init..........................................................................................112
btc_dptx_syslib_monitor................................................................................... 112
btc_dptx_test_autom........................................................................................112
btc_dptx_video_enable..................................................................................... 113
btc_dptx_mst_allocate_payload_rep................................................................... 113
btc_dptx_mst_allocate_payload_req................................................................... 114
btc_dptx_mst_clear_payload_table_rep...............................................................114
btc_dptx_mst_clear_payload_table_req...............................................................115
btc_dptx_mst_conn_stat_notify_req................................................................... 115
btc_dptx_mst_down_rep_irq..............................................................................116
btc_dptx_mst_enable....................................................................................... 116
btc_dptx_mst_enum_path_rep...........................................................................116
btc_dptx_mst_enum_path_req...........................................................................117
btc_dptx_mst_get_msg_transact_ver_rep........................................................... 117
btc_dptx_mst_get_msg_transact_ver_req........................................................... 118
btc_dptx_mst_link_address_rep......................................................................... 118
btc_dptx_mst_link_address_req......................................................................... 119
btc_dptx_mst_remote_dpcd_wr_rep................................................................... 119
btc_dptx_mst_remote_dpcd_wr_req................................................................... 120
btc_dptx_mst_remote_i2c_rd_rep...................................................................... 120
btc_dptx_mst_remote_i2c_rd_req...................................................................... 121
btc_dptx_mst_set_color_space.......................................................................... 121
btc_dptx_mst_tavgts_set.................................................................................. 122
btc_dptx_mst_up_req_irq................................................................................. 122
btc_dptx_mst_vcpid_set................................................................................... 123
btc_dptx_mst_vcptab_addvc............................................................................. 123
btc_dptx_mst_vcptab_clear............................................................................... 123
btc_dptx_mst_vcptab_delvc.............................................................................. 124
btc_dptx_mst_vcptab_update............................................................................ 124
btc_dptxll_syslib API Reference.......................................................................... 125
btc_dptxll_hpd_change..................................................................................... 125
btc_dptxll_hpd_irq........................................................................................... 125
btc_dptxll_mst_cmp_ports................................................................................ 126
btc_dptxll_mst_edid_read_rep........................................................................... 126
btc_dptxll_mst_edid_read_req........................................................................... 127
btc_dptxll_mst_get_device_ports....................................................................... 127
btc_dptxll_mst_set_csn_callback........................................................................127
btc_dptxll_mst_topology_discover...................................................................... 128
btc_dptxll_stream_allocate_rep..........................................................................128
btc_dptxll_stream_allocate_req..........................................................................129
DisplayPort Intel
®
FPGA IP User Guide
4
Contents
9.77.
9.78.
9.79.
9.80.
9.81.
9.82.
9.83.
9.84.
9.85.
9.86.
9.87.
9.88.
btc_dptxll_stream_calc_VCP_size....................................................................... 129
btc_dptxll_stream_delete_rep............................................................................ 130
btc_dptxll_stream_delete_req............................................................................ 130
btc_dptxll_stream_get...................................................................................... 131
btc_dptxll_stream_set_color_space.................................................................... 131
btc_dptxll_stream_set_pixel_rate....................................................................... 132
btc_dptxll_sw_ver............................................................................................ 132
btc_dptxll_syslib_add_tx................................................................................... 133
btc_dptxll_syslib_init........................................................................................ 133
btc_dptxll_syslib_monitor..................................................................................134
btc_dpxx_syslib Additional Types........................................................................134
btc_dprx_syslib Supported DPCD Locations..........................................................134
10. DisplayPort Source Register Map and DPCD Locations.............................................. 135
10.1. Source General Registers...................................................................................135
10.1.1. DPTX_TX_CONTROL..............................................................................135
10.1.2. DPTX_TX_STATUS................................................................................ 136
10.1.3. DPTX_TX_VERSION.............................................................................. 137
10.2. Source MSA Registers....................................................................................... 137
10.2.1. DPTX0_MSA_MVID............................................................................... 137
10.2.2. DPTX0_MSA_NVID................................................................................138
10.2.3. DPTX0_MSA_HTOTAL............................................................................ 138
10.2.4. DPTX0_MSA_VTOTAL............................................................................ 138
10.2.5. DPTX0_MSA_HSP................................................................................. 139
10.2.6. DPTX0_MSA_HSW................................................................................ 139
10.2.7. DPTX0_MSA_HSTART............................................................................ 139
10.2.8. DPTX0_MSA_VSTART............................................................................ 140
10.2.9. DPTX0_MSA_VSP................................................................................. 140
10.2.10. DPTX0_MSA_VSW...............................................................................140
10.2.11. DPTX0_MSA_HWIDTH......................................................................... 141
10.2.12. DPTX0_MSA_VHEIGHT........................................................................ 141
10.2.13. DPTX0_MSA_MISC0............................................................................ 141
10.2.14. DPTX0_MSA_MISC1............................................................................ 142
10.2.15. DPTX0_MSA_COLOR........................................................................... 142
10.2.16. DPTX0_VBID...................................................................................... 143
10.3. Source Link PHY Control and Status.................................................................... 143
10.3.1. DPTX_PRE_VOLT0.................................................................................143
10.3.2. DPTX_PRE_VOLT1.................................................................................144
10.3.3. DPTX_PRE_VOLT2.................................................................................144
10.3.4. DPTX_PRE_VOLT3.................................................................................144
10.3.5. DPTX_RECONFIG..................................................................................145
10.3.6. DPTX_TEST_80BIT_PATTERN1................................................................145
10.3.7. DPTX_TEST_80BIT_PATTERN2................................................................145
10.3.8. DPTX_TEST_80BIT_PATTERN3................................................................146
10.4. Source Timestamp............................................................................................146
10.5. Source CRC Registers....................................................................................... 146
10.6. Source Audio Registers..................................................................................... 147
10.7. Source MST Registers....................................................................................... 148
10.7.1. DPTX_MST_VCPTAB0............................................................................ 149
10.7.2. DPTX_MST_VCPTAB1............................................................................ 149
10.7.3. DPTX_MST_VCPTAB2............................................................................ 150
DisplayPort Intel
®
FPGA IP User Guide
5
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