VersaClock
®
6E Programmable
Clock Generator
5P49V6965
Datasheet
Description
The 5P49V6965 is a programmable clock generator intended for
high-performance consumer, networking, industrial, computing,
and data-communications applications. Configurations may be
stored in on-chip One-Time Programmable (OTP) memory or
changed using I
2
C interface. This is IDT’s sixth generation of
programmable clock technology (VersaClock 6E).
The frequencies are generated from a single reference clock. The
reference clock can come from one of the two redundant clock
inputs. A glitchless manual switchover function allows one of the
redundant clocks to be selected during normal operation.
Two select pins allow up to four different configurations to be
programmed and accessible using processor GPIOs or
bootstrapping. The different selections may be used for different
operating modes (full function, partial function, partial
power-down), regional standards (US, Japan, Europe) or system
production margin testing. The device may be configured to use
one of two I
2
C addresses to allow multiple devices to be used in a
system.
Features
▪
Flexible 1.8V, 2.5V, 3.3V power-rails
▪
High-performance, low phase noise PLL, < 0.5ps RMS typical
phase jitter on outputs
▪
Four banks of internal OTP memory
•
In-system or factory programmable
•
2 select pins accessible with processor GPIOs or
bootstrapping
▪
I
2
C serial programming interface
•
0xD0 or 0xD4 I2C address options allows multiple devices
configured in a same system
▪
Reference LVCMOS output clock
▪
Four universal output pairs individually configurable:
•
Differential (LVPECL, LVDS or HCSL)
•
2 single-ended (2 LVCMOS in-phase or 180 degrees out of
phase)
•
I/O V
DD
s can be mixed and matched, supporting 1.8V
(LVDS and LVCMOS), 2.5V, or 3.3V
▪
Output frequency ranges:
Typical Applications
▪
▪
▪
▪
▪
▪
▪
▪
▪
▪
Ethernet switch/router
PCI Express 1.0/2.0/3.0
Broadcast video/audio timing
Multi-function printer
Processor and FPGA clocking
Any-frequency clock conversion
MSAN/DSLAM/PON
Fiber Channel, SAN
Telecom line cards
Laser distance sensing
•
LVCMOS clock outputs: 1kHz to 200MHz
•
LVDS, LVPECL, HCSL differential clock outputs: 1kHz to
350MHz
▪
Redundant clock inputs with manual switchover
▪
Programmable output enable or power-down mode
▪
Available in 4 × 4 mm 24-VFQFPN package
▪
-40° to +85°C industrial temperature operation
Block Diagram
XIN/REF
XOUT
CLKIN
CLKINB
CLKSEL
OUT2
SD/OE
SEL1/SDA
SEL0/SCL
V
DDA
V
DDD
OTP
and
Control
Logic
FOD2
PLL
OUT2B
V
DDO
3
OUT3
FOD3
OUT3B
V
DDO
4
OUT4
FOD4
OUT4B
FOD1
OUT1B
V
DDO
2
V
DDO
0
OUT0_SEL_I2CB
V
DDO
1
OUT1
©2018 Integrated Device Technology, Inc.
1
August 31, 2018
5P49V6965 Datasheet
Contents
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
I2C Bus Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Test Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Jitter Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
PCI Express Jitter Performance and Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Features and Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Device Startup and Power-On-Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Reference Clock and Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Manual Switchover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Internal Crystal Oscillator (XIN/REF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Programmable Loop Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Fractional Output Dividers (FOD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Output Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
SD/OE Pin Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
I2C Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Typical Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Input – Driving the XIN/REF or CLKIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Output – Single-ended or Differential Clock Terminations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Package Outline Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Marking Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
©2018 Integrated Device Technology, Inc.
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5P49V6965 Datasheet
Pin Assignments
Figure 1. Pin Assignments for 4 x 4 mm 24-VFQFPN Package – Top View
OUT0_SEL_I2CB
CLKIN
CLKINB
XOUT
XIN/REF
V
DDA
CLKSEL
1
2
3
4
5
6
24 23 22
21 20
OUT1B
19
V
DDO
0
V
DDO
1
OUT1
V
DDD
18
17
V
DDO
2
OUT2
OUT2B
V
DDO
3
OUT3
OUT3B
EPAD
16
15
14
7
8
SEL1/SDA
9
SEL0/SCL
10
V
DDO
4
11
OUT4
12
13
SD/OE
4 × 4 mm 24-VFQFPN
Pin Descriptions
Table 1. Pin Descriptions
Number
1
2
3
4
5
Name
CLKIN
CLKINB
XOUT
XIN/REF
V
DDA
Input
Input
Type
Internal
Pull-down
Internal
Pull-down
Output
Input
Power
Internal
Pull-down
Internal
Pull-down
Internal
Pull-down
Internal
Pull-down
OUT4B
Description
Differential clock input. Weak 100kΩ internal pull-down.
Complementary differential clock input. Weak 100kΩ internal pull-down.
Crystal oscillator interface output.
Crystal oscillator interface input, or single-ended LVCMOS clock input. Ensure that the
input voltage is 1.2V maximum. Refer to the section
Driving XIN/REF with a CMOS Driver.
Analog functions power supply pin. Connect to 1.8V to 3.3V. V
DDA
and V
DDD
should have
the same voltage applied.
Input clock select. Selects the active input reference source in manual switchover mode.
0 = XIN/REF, XOUT (default).
1 = CLKIN, CLKINB.
See
Table 19
for more details.
Enables/disables the outputs (OE) or powers down the chip (SD).
Configuration select pin, or I
2
C SDA input as selected by OUT0_SEL_I2CB. Weak internal
pull-down resistor.
Configuration select pin, or I
2
C SCL input as selected by OUT0_SEL_I2CB. Weak internal
pull-down resistor.
6
CLKSEL
Input
7
8
9
SD/OE
SEL1/SDA
SEL0/SCL
Input
Input
Input
©2018 Integrated Device Technology, Inc.
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5P49V6965 Datasheet
Table 1. Pin Descriptions (Cont.)
Number
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Name
V
DDO
4
OUT4
OUT4B
OUT3B
OUT3
V
DDO
3
OUT2B
OUT2
V
DDO
2
OUT1B
OUT1
V
DDO
1
V
DDD
V
DDO
0
Type
Power
Output
Output
Output
Output
Power
Output
Output
Power
Output
Output
Power
Power
Power
Description
Output power supply. Connect to 1.8 to 3.3V. Sets output voltage levels for OUT4/OUT4B.
Output clock 4. Refer to the
Output Drivers
section for more details.
Complementary output clock 4. Refer to the
Output Drivers
section for more details.
Complementary output clock 3. Refer to the
Output Drivers
section for more details.
Output clock 3. Refer to the
Output Drivers
section for more details.
Output power supply. Connect to 1.8 to 3.3V. Sets output voltage levels for OUT3/OUT3B.
Complementary output clock 2. Refer to the
Output Drivers
section for more details.
Output clock 2. Refer to the
Output Drivers
section for more details.
Output power supply. Connect to 1.8 to 3.3V. Sets output voltage levels for OUT2/OUT2B.
Complementary output clock 1. Refer to the
Output Drivers
section for more details.
Output clock 1. Refer to the
Output Drivers
section for more details.
Output power supply. Connect to 1.8 to 3.3V. Sets output voltage levels for OUT1/OUT1B.
Digital functions power supply pin. Connect to 1.8 to 3.3V. V
DDA
and V
DDD
should have the
same voltage applied.
Power supply pin for OUT0_SEL_I2CB. Connect to 1.8 to 3.3V. Sets output voltage levels
for OUT0.
Latched input/LVCMOS output. At power-up, the voltage at the pin OUT0_SEL_I2CB is
latched by the part and used to select the state of pins 8 and 9. If a weak pull-up (10kΩ) is
placed on OUT0_SEL_I2CB, pins 8 and 9 will be configured as hardware select pins, SEL1
and SEL0. If a weak pull-down (10kΩ) is placed on OUT0_SEL_I2CB or it is left floating,
pins 8 and 9 will act as the SDA and SCL pins of an I
2
C interface. After power-up, the pin
acts as an LVCMOS reference output.
Connect to ground pad.
24
OUT0_SEL
_I2CB
Input/
Output
Internal
Pull-down
25
GND
GND
©2018 Integrated Device Technology, Inc.
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5P49V6965 Datasheet
Absolute Maximum Ratings
The absolute maximum ratings are stress ratings only. Stresses greater than those listed below can cause permanent damage to the
device. Functional operation of the device at absolute maximum ratings is not implied. Exposure to absolute maximum rating conditions
may affect device reliability.
Table 2. Absolute Maximum Ratings
Item
Supply Voltage, V
DDA
, V
DDD
, V
DDO
XIN/REF Input
CLKIN, CLKINB Input
I
2
C Loading Current
Storage Temperature, T
STG
ESD Human Body Model
3.6V.
1.2V.
V
DDO0
, 1.2V voltage swing.
10mA.
-65°C to 150°C.
2000V.
Rating
Thermal Characteristics
Table 3. Thermal Characteristics
Symbol
θ
JA
θ
JB
θ
JC
Parameter
Theta J
A
. Junction to air thermal impedance (0mps).
Theta J
B
. Junction to board thermal impedance (0mps).
Theta J
C
. Junction to case thermal impedance (0mps).
Value
42
2.35
41.8
Units
°C/W
°C/W
°C/W
Recommended Operating Conditions
Table 4. Recommended Operating Conditions
Symbol
Parameter
Power supply voltage for supporting 1.8V outputs.
Minimum
1.71
2.375
3.135
1.71
1.71
-40
Typical
1.8
2.5
3.3
Maximum
1.89
2.625
3.465
3.465
3.465
85
15
Units
V
V
V
V
V
°C
pF
V
DDOX
V
DDD
V
DDA
T
A
C
L
Power supply voltage for supporting 2.5V outputs.
Power supply voltage for supporting 3.3V outputs.
Power supply voltage for core logic functions.
Analog power supply voltage. Use filtered analog power supply.
Operating temperature, ambient.
Maximum load capacitance (3.3V LVCMOS only).
©2018 Integrated Device Technology, Inc.
5
August 31, 2018
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