Dual 1:4 LVDS Output 1.8V Fanout Buffer
8P34S2104
Datasheet
Description
The 8P34S2104 is a high-performance, low-power, differential
dual 1:4 LVDS Output 1.8V fanout buffer. The device is designed
for the fanout of high-frequency, very low additive phase-noise
clock and data signals. Two independent buffer channels are
available. Each channel has four low-skew outputs. High isolation
between channels minimizes noise coupling. AC characteristics
such as propagation delay are matched between channels.
Guaranteed output-to-output and part-to-part skew characteristics
make the 8P34S2104 ideal for those clock distribution
applications demanding well-defined performance and
repeatability. The device is characterized to operate from a 1.8V
power supply. The integrated bias voltage references enable easy
interfacing of AC-coupled signals to the device inputs.
Features
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Dual 1:4 low skew, low additive jitter LVDS fanout buffers
Matched AC characteristics across both channels
High isolation between channels
Low power consumption
Both differential CLKA, nCLKA and CLKB, nCLKB inputs
accept LVDS, LVPECL and single-ended LVCMOS levels
Maximum input clock frequency: 2GHz
Output amplitudes: 350mV, 500mV (selectable)
Output bank skew: 8ps typical
Output skew: 10ps typical
Low additive phase jitter, RMS: 45fs typical
(f
REF
= 156.25MHz, 12kHz - 20MHz)
Full 1.8V supply voltage mode
Device current consumption (I
DD
): 135mA typical
Lead-free (RoHS 6), 28-lead VFQFN packaging
-40°C to 85°C ambient operating temperature
Supports case temperature up to 105°C
Block Diagram
QA0
nQA0
QA1
nQA1
QA2
nQA2
QA3
nQA3
VREFA
Voltage
Reference A
VDDQB
51k
VDDQA
51k
CLKA
nCLKA
51k
51k
QB0
nQB0
QB1
nQB1
QB2
nQB2
CLKB
nCLKB
51k
51k
VDDQB
Voltage
Reference B
51k
QB3
nQB3
VREFB
SELA
8P34S2104 transistor count:
©2018 Integrated Device Technology, Inc.
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September 4, 2018
8P34S2104 Datasheet
Pin Assignments
Figure 1. Pin Assignments for 5mm x 5mm VFQFN Package – Top View
nQA3
nQA2
nQA1
V
DDQA
15
14
13
12
QA3
QA2
21
20
19
18
17
16
QB0
nQB0
QB1
nQB1
QB2
nQB2
V
DDQB
22
23
24
25
26
27
28
1
2
3
4
5
6
7
QA1
GND
nQA0
QA0
VREFA
nCLKA
CLKA
V
DDQA
8P34S2104
11
10
9
8
GND
Pin Descriptions
Table 1. Pin Descriptions
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Name
GND
QB3
nQB3
SELA
CLKB
nCLKB
VREFB
V
DDQA
CLKA
nCLKA
VREFA
QA0
nQA0
GND
V
DDQA
QA1
nQA1
Type
[a]
Power
Output
Output
Input (PU)
Input (PD)
Input (PD/PU)
Output
Power
Input (PD)
Input (PD/PU)
Output
Output
Output
Power
Power
Output
Output
Power supply ground.
VREFB
SELA
CLKB
nCLKB
nQB3
QB3
Description
Differential output B3. LVDS interface levels.
Differential output B3. LVDS interface levels.
Control input. Output amplitude select.
Non-inverting differential clock/data input for channel B.
Inverting differential clock/data input for channel B.
Bias voltage reference for CLKB, nCLKB input pairs.
Power supply pin for the channel A core input and QA[0:3] outputs.
Non-inverting differential clock/data input for channel A.
Inverting differential clock/data input for channel A.
Bias voltage reference for CLKA, nCLKA input pairs.
Differential output pair A0. LVDS interface levels.
Differential output pair A0. LVDS interface levels.
Power supply ground.
Power supply pin for the channel A core input and QA[0:3] outputs.
Differential output pair A1. LVDS interface levels.
Differential output pair A1. LVDS interface levels.
2
September 4, 2018
©2018 Integrated Device Technology, Inc.
8P34S2104 Datasheet
Table 1. Pin Descriptions (Cont.)
Number
18
19
20
21
22
23
24
25
26
27
28
ePad
[a]
Name
QA2
nQA2
QA3
nQA3
QB0
nQB0
QB1
nQB1
QB2
nQB2
V
DDQB
GND_EPAD
Type
[a]
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Power
Power
Description
Differential output pair A2. LVDS interface levels.
Differential output pair A2. LVDS interface levels.
Differential output pair A3. LVDS interface levels.
Differential output pair A3. LVDS interface levels.
Differential output pair B0. LVDS interface levels.
Differential output pair B0. LVDS interface levels.
Differential output pair B1. LVDS interface levels.
Differential output pair B1. LVDS interface levels.
Differential output pair B2. LVDS interface levels.
Differential output pair B2. LVDS interface levels.
Power supply pin for the channel B core input and QB[0:3] outputs.
Exposed pad of package. Connect to ground.
Pull-up (PU) and pull-down (PD) resistors are indicated in parentheses.
Pull-up
and
pull-down
refers to internal input resistors.
See
Table 4,
DC Input Characteristics,
for typical values.
Function Tables
Table 2. SELA Output Amplitude Selection Table
SELA
0
1 (default)
QA, QB Output Amplitude (mV)
350
500
©2018 Integrated Device Technology, Inc.
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September 4, 2018
8P34S2104 Datasheet
Absolute Maximum Ratings
NOTE:
The absolute maximum ratings are stress ratings only. Stresses greater than those listed below can cause permanent damage to
the device. Functional operation of the
8P34S2104
at absolute maximum ratings is not implied. Exposure to absolute maximum rating
conditions may affect device reliability
.
Table 3. Absolute Maximum Ratings
Item
Supply voltage, V
DD[a]
Inputs, V
I
Outputs, I
O
Continuous current
Surge current
Input sink/source, I
REF
Maximum Junction Temperature, T
J,MAX
Storage Temperature, T
STG
ESD - Human Body Model
[b]
ESD - Charged Device Model
[b]
[a]
V
DD
denotes V
DDA
, V
DDB
.
Rating
4.6V
-0.5V to V
DD[a]
+ 0.5V
10mA
15mA
±2mA
125°C
-65°C to 150°C
2000V
1500V
[b]
According to JEDEC JS-001-2012/JESD22-C101E.
DC Electrical Characteristics
Table 4. DC Input Characteristics
Symbol
C
IN
R
PULLDOWN
R
PULLUP
Parameter
Input capacitance
Input pull-down resistor
Input pull-up resistor
Test Conditions
Minimum
Typical
2
51
51
Maximum
Units
pF
k
k
Table 5. Power Supply DC Characteristics, V
DDQA
= V
DDQB
= 1.8V ± 5%, T
A
= -40°C to 85°C
Symbol
V
DDQA,
V
DDQB
I
DDQA +
I
DDQB
Parameter
Power supply voltage
Power supply
current
QA[0:3], QB[0:3]
outputs terminated
100 between nQx, Qx
Test Conditions
Minimum
1.71
Typical
1.8
175
135
Maximum
1.89
210
165
Units
V
mA
mA
500mV amplitude
350mV amplitude
©2018 Integrated Device Technology, Inc.
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September 4, 2018
8P34S2104 Datasheet
Table 6. LVCMOS Inputs DC Characteristics, V
DDQA
= V
DDQB
= 1.8V ± 5%, T
A
= -40°C to 85°C
Symbol
V
IH
V
IL
Parameter
Input high voltage
Input low voltage
Input high current
Input low current
SELA
SELA
SELA
SELA
Test Conditions
Minimum
0.65 · V
DD[a]
-0.3
Typical
Maximum
V
DD[a]
+ 0.3
0.35 · V
DD[a]
10
Units
V
V
µA
µA
I
IH
I
IL
[a]
V
IN
= V
DD[a]
= 1.89V
V
IN
= 0V, V
DD[a]
=
1.89V
-150
V
DD
denotes V
DDA
, V
DDB
.
Table 7. Differential Inputs Characteristics, V
DDQA
= V
DDQB
= 1.8V ± 5%, T
A
= -40°C to 85°C
Symbol
I
IH
Parameter
Input high current
CLKA, nCLKA
CLKB, nCLKB
CLKA, CLKB
nCLKA, nCLKB
Test Conditions
V
IN
= V
DD[a]
= 1.89V
V
IN
= 0V, V
DD[a]
=
1.89V
V
IN
= 0V, V
DD[a]
=
1.89V
I
REF
= +100µA, V
DD[a]
= 1.8V
Minimum
Typical
Maximum
150
Units
µA
µA
µA
I
IL
VREF
[a]
Input low current
Reference voltage
[b]
-10
-150
0.9
1.30
V
V
DD
denotes V
DDA
, V
DDB
.
[b]
VREF specification is applicable to the AC-coupled input interfaces shown in
Figure 5
and
Figure 6.
Table 8. LVDS DC Characteristics, V
DDQA
= V
DDQB
= 1.8V ± 5%, T
A
= -40°C to 85°C
Symbol
V
OD
V
OS
Parameter
V
OD
Magnitude Change
V
OS
Magnitude Change
Test Conditions
Minimum
Typical
Maximum
50
50
Units
mV
mV
©2018 Integrated Device Technology, Inc.
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September 4, 2018
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