DATA SHEET
SKY73212-11: 1700-2000 MHz Diversity Downconversion
Mixer with Integrated Integer-N PLL and VCO
Applications
•
Cellular base station systems: GSM/EDGE, CDMA2000, WCDMA,
TD-SCDMA
•
Other wireless communication systems
Description
Skyworks SKY73212-11 is a fully integrated diversity
downconverter that includes a high linearity mixer, large dynamic
range Intermediate Frequency (IF) amplifier, and a complete
Voltage Controlled Oscillator (VCO), synthesizer, and Local
Oscillator (LO) chain. Low loss RF baluns have also been included
to reduce design complications and to lower system cost.
The SKY73212-11 features a 3
rd
Order Input Intercept Point (IIP3)
of +24 dBm and a Noise Figure (NF) of 11 dB, which make the
device an ideal solution for high dynamic range systems such as
2G/3G base station receivers.
The SKY73212-11 also includes a fully integrated wideband
VCO/Integer-N frequency synthesizer. By applying internal VCO
division, the output LO frequency can be set to the desired value
while minimizing the phase noise.
The SKY73212-11 is controlled by a Serial Peripheral Interface
(SPI) and is manufactured using a robust silicon BiCMOS process.
The device has been designed for optimum long-term reliability. It
is manufactured in a compact, 44-pin 10 x 6 mm Multi-Chip
Module (MCM). A functional block diagram is shown in Figure 1.
The pin configuration and package are shown in Figure 2. Signal
pin assignments and functional pin descriptions are provided in
Table 1.
Features
•
RF frequency range: 1700 to 2000 MHz
•
IF frequency range: 40 to 300 MHz
•
Conversion gain: 9 dB
•
IIP3: +24 dBm; OIP3: +33 dBm
•
Noise Figure: 11 dB
•
Integrated RF balun
•
High linearity IF amplifier
•
Integer-N frequency synthesizer
•
Low phase-noise VCO
•
Low RF output comparison spurs
•
Programmable 18-bit N-counter and 11-bit R-counter
•
Wide range of reference frequencies
•
Programmable charge pump currents
•
Flexible configuration that allows connection to an external VCO
or PLL
•
Digital lock detector
•
Optional adjustment of the core, divider, and charge pump
currents by external resistor
•
Power supply for mixer: 5 V; power supply for synthesizer: 3.3 V
•
Small, low-cost MCM (44-pin, 10 x 6 mm) SMT package (MSL3,
260
°C
per JEDEC J-STD-020)
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
201390E • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • June 14, 2013
1
DATA SHEET •
SKY73212-11 MIXER WITH PLL AND VCO
Figure 1. SKY73212-11 Block Diagram
Figure 2. SKY73212-11 Pinout – 44-Pin MCM
(Top View)
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
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June 14, 2013 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • 201390E
DATA SHEET •
SKY73212-11 MIXER WITH PLL AND VCO
Table 1. SKY73212-11 Signal Descriptions
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
N/C
GND
GND
VDD_LO
GND
GND
N/C
RF_INB
VDD_MIXB
GND
IF_OUTBP
IF_OUTBN
PWRDN_B
GND
VCTRL
VDD_PLL
CP_OUT
LD_OUT
VDD_DIG
VDD_CLK
REF_CLK
Name
RF_INA
No connection
Ground
Ground
LO DC supply, +5 V
Ground
Ground
No connection
RF input, channel B
Channel B mixer DC supply, +5 V
Ground
Positive IF output, channel B
Negative IF output, channel B
Mixer power down, channel B
Ground
VCO tuning voltage
PLL supply, +3.3 V
Charge pump output
Lock detect output
Supply for digital blocks, +3.3 V
Reference buffer supply, +3.3 V
Reference clock input
Description
RF input, channel A
Pin #
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
LE
DATA
CLK
N/C
N/C
N/C
N/C
VDD_VCO
VCO_RES
GND
LO_TEST_OUT
GND
VDD_OBUF
GND
N/C
N/C
GND
PWRDN_A
IF_OUTAN
IF_OUTAP
GND
VDD_MIXA
Name
Description
Latch enable input for the SPI
Data input for the SPI
Clock input for the SPI
No connection
No connection
No connection
No connection
VCO supply, +3.3 V
External resistor to set VCO bias
Ground
LO test port
Ground
Dividers and LO buffer supply, +3.3 V
Ground
No connection
No connection
Ground
Mixer power down, channel A
Negative IF output, channel A
Positive IF output, channel A
Ground
Channel A mixer DC supply, +5 V
Functional Description
The SKY73212-11 is comprised of three main functional blocks:
•
RF balun and passive mixer
•
IF amplifier
•
Synthesizer
•
VCO
•
VCO dividers and LO chain
RF Balun and Passive Mixer
The RF baluns provide a single ended input, which can easily be
matched to 50
Ω
using a simple external matching circuit. The RF
baluns offer very low loss, and excellent amplitude and phase
balance.
The high linearity SKY73212-11 integrates a passive, double
balanced mixer that provides a very low conversion loss, and an
excellent 3
rd
Order Input Insertion Point (IIP3).
Additionally, the balanced nature of the mixer provides for high
port-to-port isolation.
LO Buffers
The LO section is optimized for low-side LO injection. The LO can
be driven over a wide frequency range with only slight
degradation in performance.
IF Amplifier
The SKY73212-11 includes high dynamic range IF amplifiers that
follow the passive mixers in the signal path. The outputs require a
supply voltage connection using inductive chokes. These choke
inductors should be high-Q and have the ability to handle 200 mA
or greater. A simple matching network allows the output ports to
be matched to a balanced 200
Ω
impedance.
The IF amplifiers are optimized for IF frequencies between 40 and
300 MHz. The IF amplifiers can be operated outside of this range,
but with a slight degradation in performance.
Mixer Power Down
A power-down function for each IF amplifier and corresponding LO
buffer is available in the SKY73212-11. The power-down function
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
201390E • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • June 14, 2013
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DATA SHEET •
SKY73212-11 MIXER WITH PLL AND VCO
is controlled through the PWRDN_A and PWRDN_B signals (pins
40 and 14, respectively):
PWRDN_A and PWRDN_B Input
High
Low
Enable/Disable
Channels A/B disabled
Channels A/B enabled
Charge Pump
The charge pump is used to convert the logic levels of the
Up
and
Dn
pulses, carrying the phase error between the reference and the
divided signal into analog quantities/current pulses.
The output of the SKY73212-11 charge pump is programmable
and varies between 1.2 mA and 7.2 mA. Additional adjustment of
the charge pump current can be accomplished by changing the
value of the external PLL bias resistor.
Lock Detector
Synthesizer
The frequency synthesizer is composed of the R-divider, N-
divider, phase detector, charge pump, and lock detector.
R-Divider
The 11-bit programmable R-divider divides the reference input
frequency and generates the reference input for the phase
detector. The R-divider range varies from 1 to 2
11
– 1(2047).
N-Divider
The lock detector circuit is activated when the phase difference
between the
Up
and
Dn
phase detector signals for a given number
of comparison cycles is shorter than a fixed delay. The CMOS
output is active high when the loop is locked. The lock detector
can be monitored from pin 19 (LD_OUT).
VCO
The VCO is designed to generate the LO signal with the tuning
function controlled by the synthesizer.
VCO Dividers and LO Chain
The divider chain consists of dividers and LO drivers. The LO
section is optimized for low-side LO injection at an RF frequency
of 1700 to 2000 MHz.
The N-divider consists of a selectable 16/17 or 32/33 prescaler,
13-bit main counter, and 5-bit swallow counter. The 18 bit N-
divider ratio is calculated as:
N=P×M–S
Where:
P
= Prescaler value
M
= Main counter value
S
= Swallow counter value
The N-divider range is from
P
2
to 2
18
– 1. For a 32/33 prescaler,
the N-divider range varies from 1024 to 262143.
Phase Detector
Digital Interface
A three-wire SPI provides mode and bias control, and control of
the PLL. The serial interface consists of three signals: the bus
clock (CLK), latch enable (LE), and the serial data line (DATA).
A write data stream consists of 25 bits:
Bits[15:0] provide the 16-bit data block.
Bits[20:16] provide the register address.
Bits[24:21] provide the device address (the SKY73212-11 is
0110b).
A timing diagram for the SPI write cycle is shown in Figure 3.
The phase detector is an edge-controlled digital circuit. The circuit
has two inputs: the reference signal (Ref) and the N-divider output.
There are two digital outputs (Up and
Dn)
that drive the charge
pump.
When the input phase difference is positive, the
Up
output is
pulled up to VDD. When the input phase difference is negative, the
Dn
output is pulled down to ground. This type of phase detector
acts only on the positive edges of the input signals.
Figure 3. SPI Write Cycles
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
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June 14, 2013 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • 201390E
DATA SHEET •
SKY73212-11 MIXER WITH PLL AND VCO
Serial Bus Timing
The SPI bus speed is programmable. Timing requirements for the
CLK, DATA, and LE signals are provided in Table 2. A serial data
input timing diagram is shown in Figure 4.
PLL Control Registers (R-Divider and N-Divider)
There are three digital PLL control registers that are used to store
the R-divider and N-divider values: R_DIV, N_DIV1, and N_DIV2.
By default, all registers are 25 bits wide. Bits[20:16] are the
address bits of the registers. The 16 least significant bits (LSBs)
represent the data bits.
Table 2. SPI Timing Requirements
Timing
t
period
t
high
t
su
t
hld
t
elch
t
width
t
efeh
Clock period
Clock high time
Data setup to clock rise
Data hold from clock rise
Enable low to clock rise
Enable high width
Clock fall to enable high
Three values are needed to calculate the three PLL dividers: the
desired frequency (F
RF
), the VCO divider (D), and the frequency
step size (F
STEP
).
The VCO frequency (F
VCO
) has a range of 2.7 GHz to 4.0 GHz, and
is defined by the product of the desired frequency (F
RF
) and the
VCO divider,
D:
F
VCO
=
F
RF
×
D
The VCO divider (equal to 1, 2, 3, 4, or 8) is chosen so that the
product of
F
RF
×
D
is within the specified VCO range.
(1)
Description
Minimum Time
(ns)
25
10
5
5
10
10
20
Figure 4. SPI Input Timing Diagram
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
201390E • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • June 14, 2013
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