S27KS0641DPBHB020 datasheet, PDF

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S27KS0641DPBHB020: DescriptionDynamic Random Access MemoryNor; Categorysemiconductor Memory IC Dynamic random access memory; File Size1MB，52 Pages; ManufacturerCypress Semiconductor; Environmental Compliance

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S27KS0641DPBHB020 Overview

Dynamic Random Access MemoryNor

S27KS0641DPBHB020 Parametric

Parameter Name	Attribute value
Maker	Cypress Semiconductor
Product Category	dynamic random access memory
type	HyperRAM
series	S27KS0641
Encapsulation	Tray
Factory packaging quantity	338

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S27KL0641/S27KS0641

S70KL1281/S70KS1281

3.0 V/1.8 V, 64 Mb (8 MB)/128 Mb (16 MB),

HyperRAM™ Self-Refresh DRAM

Distinctive Characteristics

HyperRAM™ Low Signal Count Interface

■

Up to 333 MBps

Double-Data Rate (DDR) - two data transfers per clock

166 MHz clock rate (333 MBps) at 1.8 V V

100 MHz clock rate (200 MBps) at 3.0 V V

Sequential burst transactions

Configurable Burst Characteristics

❐

Wrapped burst lengths:

• 16 bytes (8 clocks)

• 32 bytes (16 clocks)

• 64 bytes (32 clocks)

• 128 bytes (64 clocks)

❐

Linear burst

❐

Hybrid option - one wrapped burst followed by linear burst

❐

Wrapped or linear burst type selected in each transaction

❐

Configurable output drive strength

Low Power Modes

❐

Deep Power Down

Package

❐

24-ball FBGA

3.0 V I/O, 11 bus signals

❐

Single ended clock (CK)

1.8 V I/O, 12 bus signals

❐

Differential clock (CK, CK#)

Chip Select (CS#)

8-bit data bus (DQ[7:0])

Read-Write Data Strobe (RWDS)

❐

Bidirectional Data Strobe / Mask

❐

Output at the start of all transactions to indicate refresh la-

tency

❐

Output during read transactions as Read Data Strobe

❐

Input during write transactions as Write Data Mask

RWDS DCARS Timing

❐

During read transactions RWDS is offset by a second clock,

phase shifted from CK

❐

The Phase Shifted Clock is used to move the RWDS transi-

tion edge within the read data eye

■

High Performance

■

Performance Summary

Read Transaction Timings

Maximum Clock Rate at 1.8 V V

Maximum Clock Rate at 3.0 V V

Maximum Access Time, (t

ACC

at 166 MHz)

Maximum CS# Access Time to first word at

166 MHz (excluding refresh latency)

166 MHz

100 MHz

36 ns

56 ns

Maximum Current Consumption

Burst Read or Write (linear burst at 166 MHz, 1.8 V)

Power On Reset

Standby (CS# = HIGH, 3.0 V, 105 °C)

Deep Power Down (CS# = HIGH, 3.0 V, 105 °C)

Standby (CS# = HIGH, 1.8 V, 105 °C)

Deep Power Down (CS# = HIGH, 1.8 V, 105 °C)

64 MB

60 mA

50 mA

300 µA

40 µA

300 µA

20 µA

128 MB

72 mA

100 mA

600 µA

N/A

600 µA

N/A

Cypress Semiconductor Corporation

Document Number: 001-97964 Rev. *L

•

198 Champion Court

•

San Jose

CA 95134-1709

•

408-943-2600

Revised July 31, 2018

S27KL0641/S27KS0641

S70KL1281/S70KS1281

General Description

The Cypress

64-Mb HyperRAM

™

device is a high-speed CMOS, self-refresh Dynamic RAM (DRAM), with a HyperBus interface.

The Cypress 128-Mb HyperRAM is a dual-die stack of 64-Mb HyperRAM devices in a single package.

The Random Access Memory (RAM) array uses dynamic cells that require periodic refresh. Refresh control logic within the device

manages the refresh operations on the RAM array when the memory is not being actively read or written by the HyperBus interface

master (host). Since the host is not required to manage any refresh operations, the DRAM array appears to the host as though the

memory uses static cells that retain data without refresh. Hence, the memory can also be described as Pseudo Static RAM (PSRAM).

Because the DRAM cells cannot be refreshed during a read or write transaction, there is a requirement that the host not perform read

or write burst transfers that are long enough to block the necessary internal logic refresh operations when they are needed. The host

is required to limit the duration of transactions and allow additional initial access latency, at the beginning of a new transaction, if the

memory indicates a refresh operation is needed.

HyperBus is a low-signal-count, Double Data Rate (DDR) interface that achieves high-speed read and write throughput. The DDR

protocol transfers two data bytes per clock cycle on the DQ input/output signals. A read or write transaction on HyperBus consists of

a series of 16-bit wide, one clock cycle data transfers at the internal HyperRAM core with two corresponding 8-bit wide,

one-half-clock-cycle data transfers on the DQ signals. All inputs and outputs are LV-CMOS compatible. Ordering Part Number (OPN)

device versions are available for core (V

) and IO buffer (V

Q) supplies of either 1.8 V or 3.0 V (nominal).

Command, address, and data information is transferred over the eight HyperBus DQ[7:0] signals. The clock is used for information

capture by a HyperBus slave device when receiving command, address, or data on the DQ signals. Command or Address values are

center aligned with clock transitions.

Every transaction begins with the assertion of CS# and Command-Address (CA) signals, followed by the start of clock transitions to

transfer six CA bytes, followed by initial access latency and either read or write data transfers, until CS# is deasserted.

Figure 1. Read Transaction, Single Initial Latency Count

CS#

RWR

=Read Write Recovery

CK#,CK

Latency Count

RWDS

High = 2x Latency Count

Low = 1x Latency Count

RWDS and Data

are edge aligned

DQ[7:0]

47:40

39:32

31:24

23:16

15:8

7:0

Dn+1

ACC

= Access

Command-Address

Host drives DQ[7:0] and Memory drives RWDS

Memory drives DQ[7:0]

and RWDS

The Read/Write Data Strobe (RWDS) is a bidirectional signal that indicates:

■

when data will start to transfer from a HyperRAM device to the master device in read transactions (initial read latency)

when data is being transferred from a HyperRAM device to the master device during read transactions (as a source synchronous

read data strobe)

when data may start to transfer from the master device to a HyperRAM device in write transactions (initial write latency)

data masking during write data transfers

During the CA transfer portion of a read or write transaction, RWDS acts as an output from a HyperRAM device to indicate whether

additional initial access latency is needed in the transaction.

During read data transfers, RWDS is a read data strobe with data values edge aligned with the transitions of RWDS.

Document Number: 001-97964 Rev. *L

Page 5 of 51

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