TQP3M9036
®
Ultra-Low Noise, High Linearity LNA
Product Overview
The TQP3M9036 is a high linearity, ultra-low noise gain
block amplifier in a small 2x2 mm surface-mount package.
At 900 MHz, the amplifier typically provides high 19.8 dB
gain, +36 dBm OIP3, and 0.45 dB Noise Figure while
drawing 68 mA current from a 5V supply. The amplifier
does not require any negative supplies for operation and
can be biased from positive supply rails from 3.3 to 5 V.
The device is housed in a lead-free/green/RoHS-compliant
industry-standard 2x2 mm package.
The TQP3M9036 is internally matched using a high-
performance E-pHEMT process and only requires 4
external components for operation from a single positive
supply: an external RF choke and blocking/bypass
capacitors. The low noise amplifier contains an internal
active bias to maintain high performance over temperature
and integrates a shut-down biasing capability for TDD
applications.
The TQP3M9036 covers the 50−2000 MHz frequency band
and is targeted for wireless infrastructure. The LNA is pin
compatible with the high-band, 1500−2700 MHz
TQP3M9037.
8-pin 2x2 mm DFN Package
Key Features
•
50−2000 MHz Operational Bandwidth
•
Ultra-low noise figure, 0.45 dB NF at 900 MHz
•
High gain, 19.8 dB Gain at 900 MHz
•
High linearity, +36 dBm Output IP3
•
High input power ruggedness, >22 dBm P
IN, MAX
•
Unconditionally stable
•
Integrated on-chip matching, 50 ohm in/out
•
Integrated active bias
•
Integrated shutdown control pin
•
3-5 V positive supply voltage: −Vgg not required
•
Pin compatible with high-band TQP3M9037
Functional Block Diagram
Pin 1 Reference Mark
Applications
•
•
•
•
•
Repeaters
Mobile Infrastructure
LTE / WCDMA / CDMA / GSM
General Purpose Wireless
TDD or FDD systems
NC
RF In
NC
NC
1
2
3
4
8
7
6
5
NC
RF Out
Shut Down
NC
Backside Paddle - RF/DC GND
Top View
Ordering Information
Part No.
TQP3M9036
TQP3M9036−PCB
Description
Ultra low noise, High IP3 LNA
100−2000 MHz Evaluation Board
Standard T/R size = 2500 pieces on a 7” reel
Datasheet, November 27, 2018 | Subject to change without notice
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TQP3M9036
®
Ultra-Low Noise, High Linearity LNA
Absolute Maximum Ratings
Parameter
Storage Temperature
RF Input Power,
CW, 50 Ω, T=+25 °C
Device Voltage (V
DD
)
Rating
−65 to 150 °C
+22 dBm
+7 V
Recommended Operating Conditions
Parameter
Device Voltage (V
CC
)
T
CASE
Tj for >10
6
hours MTTF
Min
+3.3
−40
Typ
+5.0
Max Units
+5.25
+105
+190
V
°C
°C
Operation of this device outside the parameter ranges given
above may cause permanent damage.
Electrical specifications are measured at specified test conditions.
Specifications are not guaranteed over all recommended operating
conditions.
Electrical Specifications
Test conditions unless otherwise noted:
V
DD
= +5V, Temp=+25°C, 50 Ω system.
Parameter
Operational Frequency Range
Test Frequency
Gain
Input Return Loss
Output Return Loss
Output P1dB
Output IP3
Noise Figure
Power Shutdown Control
(3)
Current, I
DD
Shutdown pin current, I
SD
Switching Speed
(4)
Thermal Resistance, θ
jc
Conditions
Min
50
18.2
Typ
900
19.8
13
11
+20
+36
0.45
3.3
68
3
140
1
0.5
62
Max
2000
21.2
Units
MHz
MHz
dB
dB
dB
dBm
dBm
dB
V
V
mA
mA
µA
µs
µs
°C/W
Note 1
Note 1
Pout=+5 dBm/tone, Δf=1 MHz
On state
Off state (Power down)
On state
Off state (Power down)
V
PD
≥ 3 V
ON time (50%Ctrl to 90% RF)
OFF time (50%Ctrl to 10% RF)
channel to case
+32
0
2.5
40
0.75
0.4
V
DD
90
4
Notes:
1. Input and output return loss can be improved to better than 15 dB with minimal impact on noise figure by adjusting the values of
the bias inductor and output DC blocking capacitor. Refer to the Optimized Return Loss reference design on page 7.
2. Current can be reduced by operating at a lower device voltage. (example: I
dd
=50 mA at V
dd
=4 V)
3. Voltage referred to J5 turret on evaluation board (pg.4).
4. Switching speed can be improved by reducing the value of C1 of schematic on pg. 4.
Pin 6 (V
PD
) voltage limits
V
low
V
high
min
0
0.5
Max
0.1
V
DD
Units
V
V
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TQP3M9036
®
Ultra-Low Noise, High Linearity LNA
Device Characterization Data
S-Parameters
Test conditions unless otherwise noted: V
DD
=+5 V, I
DD
=68 mA (typ.), Temp=+25°C, 50 Ohm system
Freq (MHz)
S11 (dB)
S11 (ang)
S21 (dB)
S21 (ang)
S12 (dB)
S12 (ang)
S22 (dB)
S22 (ang)
50
100
200
400
600
800
1000
1200
1400
1600
1800
2000
2200
2400
2600
2800
-7.1
-7.3
-8.0
-9.8
-11.4
-12.6
-13.6
-14.4
-14.9
-15.4
-15.7
-15.9
-16.2
-16.4
-16.7
-16.9
-11.1
-13.5
-20.6
-30.6
-34.6
-36.2
-36.1
-35.7
-34.8
-33.9
-33.2
-32.6
-32.1
-31.3
-30.5
-29.6
28.4
28.1
27.2
24.8
22.5
20.6
19.0
17.6
16.4
15.4
14.4
13.6
12.8
12.1
11.5
10.9
167.9
160.6
145.9
124.1
109.8
99.5
91.3
84.4
78.3
72.7
67.6
62.8
58.2
53.8
49.5
45.3
-33.8
-33.5
-32.6
-30.1
-27.5
-25.4
-23.7
-22.2
-20.9
-19.9
-18.9
-18.0
-17.2
-16.4
-15.8
-15.1
13.3
16.7
28.7
45.5
53.1
56.2
56.8
56.4
55.1
53.4
51.4
49.3
47.0
44.6
42.0
39.4
-22.8
-20.1
-15.8
-12.4
-11.3
-10.9
-10.6
-10.5
-10.4
-10.3
-10.2
-10.2
-10.2
-10.2
-10.2
-10.3
-2.8
27.8
32.8
17.7
4.5
-5.8
-14.5
-22.1
-29.2
-35.6
-41.6
-47.2
-52.9
-58.3
-63.6
-69.2
Noise Parameters
Test conditions unless otherwise noted: V
DD
=+5 V, I
DD
=68 mA (typ.), Temp=+25°C, 50 Ohm system
Freq (MHz)
NF
min
(dB)
MagOpt (mag)
AngOpt (deg)
Rn (Ω)
700
900
1100
1300
1500
1700
0.356
0.452
0.415
0.406
0.377
0.346
0.187
0.174
0.140
0.142
0.116
0.115
10.9
22.2
12.1
23.7
-6.64
23.6
0.062
0.060
0.061
0.062
0.069
0.062
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TQP3M9036
®
Ultra-Low Noise, High Linearity LNA
Application Circuit – TQP3M9036-PCB
J5
J4
J3
C4
J3 V
DD
1 uF
R
3
J4 GND
C4
C3
L1
C3
C1
U1
R2
R1
C2
J1
RF
Input
C1
2
100 pF
L1
68 nH
(0603) C2
Q1
6
1,3,4,5,8
7
J2
RF
Output
100 pF
100 pF
R2
33k
J5 P
D
C5
C6
R1
10k
See note 6. Resistors are
not needed if shut-down
functionality is not used.
Notes:
1.
See Evaluation Board PCB Information section for material and stack-up.
2.
R3 (0 Ω jumper) is not shown on the schematic and may be replaced with copper trace in the target application layout.
3.
All components are of 0402 size unless stated on the schematic.
4.
C1, C2, and C3 are non-critical values. The reactive impedance should be as low as possible at the frequency of operation for
optimal performance.
5.
The L1 value is non-critical and needs to provide high reactive impedance at the frequency of operation.
6.
R1 and R2 are optional and do not need to be loaded if the shut-down functionality is not needed; i.e. FDD applications.
If R1 and R2 are not loaded, the LNA will operate in its standard “ON” state.
7.
A through line is included on the evaluation board for board loss measurement and de-embedding.
Bill of Material − TQP3M9036-PCB
Reference Des.
-
U1
R1
R2
R3
L1
C4
C1, C2, C3, C5, C6
J3, J4, J5
Value
-
-
10K Ω
33K Ω
0Ω
68 nH
1.0 μF
100 pF
-
Description
PCB, Printed Circuit Board
AMP, Ultra-Low Noise, High Linearity
RES, 0402, 5%, 1/16W
RES, 0402, 5%, 1/16W
RES, 0402, 5%, 1/16W
IND, 0603, 5%, Ceramic
CAP, 0402, 10%, 10V, X5R
CAP, 0402, 5%, 50V, NPO/COG
Solder Turret
Manuf.
Qorvo
Qorvo
various
various
various
various
various
various
various
Part Number
1084112
TQP3M9036
various
various
various
various
various
various
various
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TQP3M9036
®
Ultra-Low Noise, High Linearity LNA
Γopt and S11*
TQP3M9036
0.8
1.0
Conj(S(1,1))
Swp Max
0.91GHz
GMN()
2.
0
6
0.
0.
4
0
3.
0
4.
5.0
S
11
*
10.0
0.2
0.4
0.6
0.8
1.0
2.0
3.0
4.0
5.0
0
.4
-0
-0
.6
-0.8
.0
-2
Swp Min
0.9GHz
-1.0
Datasheet, November 27, 2018 | Subject to change without notice
5 of 12
-4
.0
-5.
0
2
-0.
-10.0
-3
.0
0.2
10.0
Γ
OPT
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