Low Phase-Noise, Low-Power
Programmable PhiClock™ Generator
9FGV1005
Datasheet
Description
The 9FGV1005 is a member of IDT's PhiClock™ programmable
clock generator family. The 9FGV1005 provides two copies of a
single non-spread spectrum output frequency and one copy of the
crystal reference input. Two select pins allow for hardware
selection of the desired configuration, or two I
2
C bits allow easy
software selection of the desired configuration. The user may
configure any one of the four OTP configurations as the default
when operating in I
2
C mode. Four unique I
2
C addresses are
available, allowing easy I
2
C access to multiple components.
Features
▪
1.8V to 3.3V operation
▪
Individual 1.8V to 3.3V V
DDO
for each programmable output
pair
▪
Supports HCSL, LVDS and LVCMOS I/O standards
▪
Supports LVPECL and CML logic with easy AC coupling – see
application note
AN-891
for alternate terminations
▪
HCSL utilizes IDT's LP-HCSL technology for improved
performance, lower power and higher integration:
— Programmable output impedance of 85 or 100Ω
▪
On-board OTP supports up to 4 complete configurations
▪
Configuration selected via strapping pins or I
2
C
▪
< 100mW at 1.8V, < 200mW at 3.3V (LP-HCSL outputs running
at 100MHz)
▪
4 programmable I
2
C addresses: D0/D1, D2/D3, D4/D5, D6/D7
read/write
▪
Supported by IDT
Timing Commander™
software
▪
3 × 3 mm 16-LGA with integrated crystal option (9FGV1005Q)
Typical Applications
▪
▪
▪
▪
▪
▪
HPC
Storage
10G/25G Ethernet
Fiber Optic Modules
SSDs
NVLink
Output Features
▪
▪
▪
▪
1 integer output frequency per configuration
2 programmable output pairs plus 1 LVCMOS REF output
10MHz–325MHz output frequency (LVDS or LP-HCSL)
10MHz–200MHz output frequency (LVCMOS)
Key Specifications
▪
259fs rms typical phase jitter outputs at 156.25MHz (12kHz–
20MHz)
▪
PCIe Gen1–4 compliant
PCIe Clocking Architectures
Block Diagram
VDDDp
XIN/CLKIN
XO
OSC
OTP_VPP
▪
Common Clocked (CC)
▪
Independent Reference without spread spectrum (SRnS)
VDDAp
REF0
VDDREFp
INT
PLL
INT
DIV
OUT1#
OUT1
VDDO1
OUT0#
OUT0
VDDO0
vSEL_I2C#
^SEL0/SCL
^SEL1/SDA
SMBus
Engine
Factory
Configuration
Control Logic
Internal terminations are available when LP -HCSL output format is selected.
EPAD/GND
©2018 Integrated Device Technology, Inc.
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9FGV1005 Datasheet
Pin Assignments
Figure 1. Pin Assignments for 3 x 3 mm 16-LGA Package – Top View
vREF0_SEL_I2C#
vREF0_SEL_I2C#
VDDREFp
VDDREFp
VDDO1
VDDAp
16 15 14 13
XIN/CLKIN 1
XO 2
^SEL0/SCL 3
^SEL1/SDA 4
5
VDDDp
6
OTP_VPP
7
OUT0#
8
OUT0
9FGV1005
Connect EPAD to
GND
16 15 14 13
12 OUT1
11 OUT1#
10 NC
9 VDDO0
NC 1
NC 2
^SEL0/SCL 3
^SEL1/SDA 4
VDDO1
12 OUT1
11 OUT1#
10 NC
9 VDDO0
8
OUT0
9FGV1005Q
Connect EPAD to
GND
5
VDDDp
6
OTP_VPP
16-LGA 3 x 3 mm, 0.5mm pitch
^ prefix indicates internal pull-up resistor
v prefix indicates internal pull-down resistor
16-LGA 3 x 3 mm, 0.5mm pitch
^ prefix indicates internal pull-up resistor
v prefix indicates internal pull-down resistor
Pin Descriptions
Table 1. Pin Descriptions
Number
1
[a]
2
[a]
3
4
5
6
7
8
9
10
11
12
13
XO
Name
XIN/CLKIN
Type
Input
Output
Input
I/O
Power
Power
Output
Output
Power
—
Output
Output
Power
Crystal output.
Description
Crystal input or reference clock input.
Select pin for internal frequency configurations/I
2
C clock pin. Function is determined
by state of SEL_I2C# upon power-up. This pin has an internal pull-up.
Select pin for internal frequency configurations/I
2
C data pin. Function is determined by
state of SEL_I2C# upon power-up. This pin has an internal pull-up.
Digital power. 1.8V to 3.3V. V
DDAp
and V
DDDp
should be connected to the same power
supply.
Voltage for programming OTP. During normal operation, this pin should be connected
to the same power rail as V
DDD
.
Complementary output clock 0.
Output clock 0.
Power supply for output 0.
No connect.
Complementary output clock 1.
Output clock 1.
Power supply for output 1.
^SEL0/SCL
^SEL1/SDA
V
DDDp
OTP_VPP
OUT0#
OUT0
V
DDO0
NC
OUT1#
OUT1
V
DDO1
©2018 Integrated Device Technology, Inc.
2
OUT0#
VDDAp
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9FGV1005 Datasheet
Table 1. Pin Descriptions (Cont.)
Number
14
V
DDAp
Name
Type
Power
Description
Power supply for analog circuits. V
DDAp
and V
DDDp
should be connected to the same
power supply. Programmable for nominal voltages of 1.8V, 2.5V or 3.3V.
15
vREF0_SEL_I2C#
Latched input/LVCMOS output. At power-up, the state of this pin is latched to select
the state of the I
2
C pins. After power-up, the pin acts as an LVCMOS reference output.
Latched This pin has an internal pull-down.
I/O
1 = SEL0/SEL1.
0 = SCL/SDA.
Power
GND
Power supply for REF0 and REF1 and the internal XO. Programmable to 1.8V, 2.5V or
3.3V.
Connect to ground.
16
17
[a]
V
DDREFp
EPAD
Note:
Unused outputs can be programmed off and left floating. V
DDREF
and V
DDO0
have to be connected.
These pins are 'No Connect' on 9FGV1005Q integrated quartz versions. See
Pin Assignments
diagram for 9FGV1005Q.
©2018 Integrated Device Technology, Inc.
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9FGV1005 Datasheet
Absolute Maximum Ratings
The absolute maximum ratings are stress ratings only. Stresses greater than those listed below can cause permanent damage to the
device. Functional operation of the 9FGV1005 at absolute maximum ratings is not implied. Exposure to absolute maximum rating
conditions may affect device reliability.
Table 2. Absolute Maximum Ratings
Parameter
Rating
Supply Voltage, V
DDA
, V
DDD
, V
DDO
Storage Temperature, T
STG
ESD Human Body Model
Junction Temperature
Inputs
XIN/CLKIN
Other Inputs
Outputs
Outputs, V
DDO
(LVCMOS)
Outputs, IO (SDA)
3.465V
-65°C to 150°C
2000V
125°C
0V to 1.2V voltage swing
-0.5V to V
DDD
-0.5V to V
DDO
+ 0.5V
10mA
Thermal Characteristics
Table 3. Thermal Characteristics
1
Parameter
Symbol
θ
JC
θ
Jb
Conditions
Junction to case.
Junction to base.
Junction to air, still air.
Junction to air, 1 m/s air flow.
Junction to air, 3 m/s air flow.
Junction to air, 5 m/s air flow.
Junction to case.
Junction to base.
Junction to air, still air.
Junction to air, 1 m/s air flow.
Junction to air, 3 m/s air flow.
Package
Typical Values
66
5.1
63
56
51
49
82.1
42.3
Units
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
Notes
1
1
1
1
1
1
1
1
1
1
1
Thermal Resistance
(devices with external crystal)
θ
JA0
θ
JA1
θ
JA3
θ
JA5
θ
JC
θ
Jb
θ
JA0
θ
JA1
θ
JA3
LTG16
Thermal Resistance
Q-series (devices with internal
crystal)
LTG16
93.6
87.1
83.3
1
EPAD soldered to board.
©2018 Integrated Device Technology, Inc.
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9FGV1005 Datasheet
Recommended Operating Conditions
Table 4. Recommended Operating Conditions
Symbol
V
DDOx
V
DDD
V
DDA
T
A
C
L
t
PU
Parameter
Power supply voltage for supporting 1.8V outputs.
Power supply voltage for supporting 2.5V outputs.
Power supply voltage for supporting 3.3V outputs.
Power supply voltage for core logic functions.
Analog power supply voltage. Use filtered analog power supply if
available.
Operating temperature, ambient.
Maximum load capacitance (3.3V LVCMOS only).
Power-up time for all V
DD
s to reach minimum specified voltage (power
ramps must be monotonic).
Minimum
1.71
2.375
3.135
1.71
1.71
-40
Typical
1.8
2.5
3.3
Maximum Units
1.89
2.625
3.465
3.465
3.465
85
15
V
V
V
V
V
°C
pF
ms
0.05
5
Electrical Characteristics
V
DDx
= 3.3V ±5%, 2.5V ±5%, 1.8V ±5%, T
A
= -40°C to +85°C unless stated otherwise.
Table 5. Common Electrical Characteristics
Parameter
Symbol
Conditions
Minimum
Typical
Maximum
Units
Notes
Input Frequency
Output Frequency
VCO Frequency
Loop Bandwidth
Input High Voltage
Input Low Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
Input Low Voltage
Input Rise/Fall Time
Input Capacitance
Internal Pull-up
Resistor
Internal Pull-down
Resistor
f
IN
f
OUT
f
VCO
f
BW
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
T
R
/T
F
C
IN
R
UP
R
DOWN
Crystal input frequency.
CLKIN input frequency.
Differential clock output.
Single-ended clock output.
VCO operating frequency range.
Input frequency = 25MHz.
SEL[1:0].
SEL[1:0].
REF/SEL_I2C#.
REF/SEL_I2C#.
XIN/CLKIN.
XIN/CLKIN.
SEL1/SDA, SEL0/SCL.
SEL[1:0].
SEL[1:0] at 25°C.
REF/SEL_I2C#.
8
1
10
10
2400
0.06
0.7 x V
DDD
GND - 0.3
0.65 x V
DDREF
-0.3
0.8
-0.3
3
200
200
237
237
2500
50
240
325
200
2600
0.9
V
DDD
+ 0.3
0.8
V
DDREF
+ 0.3
0.4
1.2
0.4
300
7
300
300
MHz
MHz
MHz
MHz
MHz
MHz
V
V
V
V
V
V
ns
pF
kΩ
kΩ
1
5
©2018 Integrated Device Technology, Inc.
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May 30, 2018
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