Features
Datasheet
RX63T Group
Renesas MCUs
100-MHz 32-bit RX MCU, on-chip FPU, 165 DMIPS,
Two 12-bit ADCs (three S/H circuits, double data registers, amplifier, comparator), one 10-bit ADC, simultaneous
sampling on 7 channels using three ADCs, 100 MHz PWM (2 three-phase complementary channels + 4 single-phase
complementary channels or 3 three-phase complementary channels + 1 single-phase complementary channel)
R01DS0087EJ0220
Rev.2.20
Mar 31, 2016
Features
■
32-bit RX CPU core
Max. operating frequency: 100 MHz
Capable of 165 DMIPS in operation at 100 MHz
Single precision 32-bit IEEE-754 floating point
Two types of multiply-and-accumulation unit (between memories
and between registers)
32-bit multiplier (fastest instruction execution takes one CPU clock
cycle)
Divider (fastest instruction execution takes two CPU clock cycles)
Fast interrupt
CISC Harvard architecture with 5-stage pipeline
Variable-length instructions: Ultra-compact code
Supports the memory protection unit (MPU)
Two types of debugging interfaces: JTAG and FINE (two-line)
Single 3.3-V supply or single 5-V supply; 3.3-V products can be
used with a 5-V analog power supply
Four low-power modes
100-MHz operation, 10-ns read cycle (no wait states)
Max. 512 Kbytes
User code is programmable by USB, SCI, or JTAG.
PLQP0144KA-A
PLQP0120KA-A
PLQP0112JA-A
PLQP0100KB-A
PLQP0064KB-A
PLQP0048KB-A
20 × 20mm, 0.5mm pitch
16 × 16mm, 0.5mm pitch
20 × 20mm, 0.65mm pitch
14 × 14mm, 0.5mm pitch
10 × 10mm, 0.5mm pitch
7 × 7mm, 0.5mm pitch
■
Up to 11 communications interfaces
■
Low-power design and architecture
■
On-chip main flash memory, no wait states
■
On-chip data flash memory
USB 2.0 full-speed function interface (1 channel)
CAN (compliant with ISO11898-1), incorporating 32 mailboxes (1
channel)
SCI with multiple functionalities (5 channels)
Choose from among asynchronous mode, clock-synchronous mode,
smart-card interface mode, simple SPI, simple I
2
C, and extended
serial mode.
I
2
C bus interface for SMBus (2 channels)
RSPI for high-speed transfer (2 channels)
16-bit MTU3: 100-MHz operation, input capture, output compare,
three-phase complementary PWM waveform output (2 channels),
phase-counting mode (8 channels); complementary PWM does not
burden the CPU.
16-bit GPT: 100-MHz operation, input capture, output compare, 4-
channel single-phase complementary PWM waveform output or 1-
channel three-phase complementary + 1-channel single-phase
complementary output, interlocking with comparator (counter
operation, PWM negation control), detection of abnormal oscillation
frequencies (useful for IEC60730 compliance)
(8 channels); complementary PWM does not burden the CPU.
16-bit CMT (4 channels)
Max. 32 Kbytes, reprogrammable up to 100,000 times
Programming/erasing as background operations (BGOs)
Max. 48 Kbytes
For instructions and operands
■
Up to twenty 16-bit timers
■
On-chip SRAM, no wait states
■
DMA
DMA: Incorporates four channels
DTC: A single unit can handle transfer on multiple channels.
Power-on reset (POR)
Low voltage detection (LVD) with voltage settings
External crystal oscillator or internal PLL for operation at 4 to 12.5
MHz
Internal 125-kHz LOCO
Dedicated 125-kHz LOCO for the IWDT
125-kHz LOCO clock operation
■
Reset and supply management
■
Clock functions
■
Generation of delays in PWM waveforms (for
products with the product ID code 1)
The timing with which signals on the 16-bit GPT PWM output pin
rise and fall can be controlled with an accuracy of up to 312 ps (in
operation at 100 MHz).
■
Independent watchdog timer
■
Useful functions for IEC60730 compliance
■
External address space
Oscillation-stop detection, frequency measurement, CRC, IWDT,
self-diagnostic function for the A/D converter, etc.
4 CS areas (4 × 1 Mbyte)
Multiplexed address data or separate address lines are selectable per
area.
8- or 16-bit bus space is selectable per area.
■
Two A/D converters for 1-MHz operation, total of 8
channels
Simultaneous sampling on 7 channels is possible with three units.
Self-diagnosis function (useful for IEC60730 compliance)
Two 12-bit ADCs: three sample-and-hold circuits, double data
registers, amplifier, comparator (8 channels)
One 10-bit ADC (12 channels)
■
One A/D converter for 2-MHz operation, total of 20
channels
One 10-bit ADC (20 channels)
■
10-bit D/A converter: 2 channels
■
Digital Power Supply Controller-Dedicated
Calculation Function (for products with product ID
code 1)
16-bit fixed-point calculation function that handles compensatory
calculations in the method of digital control for switched-mode
power supplies.
■
Register write protection function can protect values
in important registers against overwriting.
■
Up to 110 pins for GPIO
Open drain, switchable driving ability
■
Operating temp. range
–40C to +85C
–40C to +105C
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Page 1 of 186
RX63T Group
1. Overview
1.
1.1
Overview
Outline of Specifications
Table 1.1
lists the specifications in outline, and
Table 1.2
lists the functions of products.
Table 1.1
shows an outline of the maximum specifications, and the available peripheral modules and number of
channels differ according to the number of pins on the package and the ROM capacity. For details, see
Table 1.2,
Comparison of Functions for Different Packages.
Table 1.1
Classification
CPU
Outline of Specifications (1/7)
Module/Function
CPU
Description
Maximum operating frequency: 100 MHz
32-bit RX CPU
Minimum instruction execution time: One instruction per state (cycle of the system
clock)
Address space: 4-Gbyte linear
Register set of the CPU
General purpose: Sixteen 32-bit registers
Control: Nine 32-bit registers
Accumulator: One 64-bit register
Basic instructions: 73
Floating-point operation instructions: 8
DSP instructions: 9
Addressing modes: 10
Data arrangement
Instructions: Little endian
Data: Selectable as little endian or big endian
On-chip 32-bit multiplier: 32 × 32
64 bits
On-chip divider: 32 / 32
32 bits
Barrel shifter: 32 bits
Memory protection unit (MPU)
Single precision floating point (32 bits)
Data types and floating-point exceptions in conformance with the IEEE754 standard
Capacity: 512 Kbytes, 384 Kbytes, 256 Kbytes, 64 Kbytes, 48 Kbytes, 32 Kbytes
100 MHz, no-wait access
On-board programming: Programs can be modified through SCI or USB while the MCU
is mounted on the board.
Off-board programming: Programs can be modified using parallel programmer.
(only in 144-, 120-, 112- and 100-pin versions)
Capacity: 48 Kbytes, 32 Kbytes, 24 Kbytes, 8 Kbytes
100 MHz, no-wait access
Capacity: 32 Kbytes, 8 Kbytes
Programming/erasing: 100,000 times
On-board programming:
Programs can be modified through SCI or USB while the MCU is mounted on the board.
Programming from the user program is possible.
[144-, 120-, 112- and 100-pin versions]
Single-chip mode, on-chip ROM enabled extended mode, on-chip ROM disabled
extended mode (switchable by software)
[64- and 48-pin versions]
Single-chip mode
FPU
Memory
ROM
RAM
E
2
data flash
MCU operating modes
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
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RX63T Group
Table 1.1
Classification
Clock
1. Overview
Outline of Specifications (2/7)
Module/Function
Clock generation circuit
Description
Main clock oscillator, low-speed on-chip oscillator, PLL frequency synthesizer, and
dedicated on-chip oscillator for the IWDT
Main-clock oscillation stop detection
Separate frequency-division and multiplication settings for the system clock (ICLK),
peripheral module clock (PCLKA), peripheral module clock (PCLKB), AD clock
(PCLKC), FlashIF clock (FCLK) and S12AD clock (PCLKD).
The CPU and other bus masters run in synchronization with the system clock (ICLK):
Up to 100 MHz
Multi-function timer pulse unit 3 and general PWM timer run in synchronization with
PCLKA: Up to 100 MHz
Peripheral modules run in synchronization with the peripheral module clock (PCLKB):
Up to 50 MHz
Flash IF run in synchronization with the FlashIF clock (FCLK): Up to 50 MHz
Devices connected to the external bus run in synchronization with the external bus
clock (BCLK): Up to 50 MHz
10-bit A/D converter runs in synchronization with the AD clock (PCLKC): Up to 100 MHz
12-bit A/D converter runs in synchronization with the S12AD clock (PCLKD): Up to 50
MHz
The frequency of the following clocks can be measured; the main clock oscillator, PLL
circuit, and IWDT-dedicated on-chip oscillator.
RES# pin reset, power-on reset, voltage-monitoring reset, independent watchdog timer
reset, watchdog timer reset, deep software standby reset, and software reset
When the voltage on VCC passes the voltage detection level (Vdet), an internal reset or
internal interrupt is generated.
Module stop function
Four low power consumption modes
Sleep mode, all-module clock stop mode, software standby mode, and deep software
standby mode
Peripheral function interrupts: Up to 169 sources
External interrupts: Up to 8 (pins IRQ0 to IRQ7)
Software interrupts: One source
Non-maskable interrupts: 6 sources
Sixteen levels specifiable for the order of priority
Clock
Clock frequency
accuracy measurement
circuit (CAC)
Reset
Voltage detection circuit
Low power
consumption
Low power
consumption facilities
Interrupt
Interrupt controller
(ICUb)
External bus extension
The external address space can be divided into four areas (CS0 to CS3), each with
independent control of access settings.
Capacity of each area: 1 Mbyte (CS0 to CS3)
A chip-select signal (CS0# to CS3#) can be output for each area.
Each area is specifiable as an 8- or 16-bit bus space
The data arrangement in each area is selectable as little or big endian (only for data).
Bus format: Separate bus, multiplex bus
Wait control
Write buffer facility
4 channels
Three transfer modes: Normal transfer, repeat transfer, and block transfer
Activation sources: Software trigger, external interrupts, and interrupt requests from
peripheral functions
Three transfer modes: Normal transfer, repeat transfer, and block transfer
Activation sources: Software interrupt activation register settings, external interrupts,
and interrupt requests from peripheral functions
DMA
DMA controller
(DMACA)
Data transfer controller
(DTCa)
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
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RX63T Group
Table 1.1
Classification
I/O ports
1. Overview
Outline of Specifications (3/7)
Module/Function
General I/O ports
Description
144-pin LQFP
I/O pins: 81
Input pins: 29
Open-drain outputs: 27
120-pin LQFP
I/O pins: 72
Input pin: 21
Open-drain outputs: 26
112-pin LQFP
I/O pins: 69
Input pins: 21
Open-drain outputs: 20
100-pin LQFP
I/O pins: 57
Input pins: 21
Open-drain outputs: 16
64-pin LQFP
I/O pins: 39
Input pins: 9
Open-drain outputs: 10
5-V tolerance: 39
48-pin LQFP
I/O pins: 25
Input pins: 7
Open-drain outputs: 8
5-V tolerance: 25
(16 bits × 8 channels)
Maximum of 16 pulse-input/output and 3 pulse-input possible
Select eight clocks from among ten count clocks (PCLKA/1, PCLKA/4, PCLKA/16,
PCLKA/64, PCLKA/256, PCLKA/1024, MTCLKA, MTCLKB, MTCLKC, and MTCLKD)
for each channel (seven clocks for channel 1, four clocks for channel 5, and six clocks
for channel 6 or 7)
24 output compare/input capture registers
Counter-clearing operation (simultaneous clearing on compare match or input capture)
Simultaneous writing to multiple timer counters (TCNT)
Simultaneous input and output to registers in synchronization with counter operations
Buffer operation specifiable
Capable of cascade-connected operation
Interrupts: 38 sources
Automatic transfer of register data
Pulse output modes
Topple, PWM, complementary PWM, and reset-synchronous PWM modes
Complementary PWM output mode
Outputs non-overlapping waveforms for controlling 3-phase inverters
Automatic specification of dead times
PWM duty cycle: Selectable as any value from 0% to 100%
Delay can be applied to requests for A/D conversion.
Non-generation of interrupt requests at peak or trough values of counters can be
selected.
Double buffering
Reset-synchronous PWM mode
Three PWM waveforms and corresponding inverse waveforms are output with the
desired duty cycles.
Phase-counting mode
Counter functionality for dead-time compensation
Generation of triggers for A/D converters
Differential timing for initiation of A/D conversion
Control of the high-impedance state of the MTU3 and GPT’s waveform output pins
Six pins for input from signal sources: POE0, POE4, POE8, POE10, POE11, and
POE12
Initiation on detection of short-circuited outputs (detection of PWM outputs having
simultaneously become an active level.)
Initiation by comparator-detection, oscillation-stoppage detection, or software
Software control of the states of pins for output control can also be added.
Timers
Multi-function timer
pulse unit 3 (MTU3)
Port output enable 3
(POE3)
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Page 4 of 186
RX63T Group
Table 1.1
Classification
Timers
1. Overview
Outline of Specifications (4/7)
Module/Function
General PWM timer
(GPT)
Description
16 bits x 8 channels
Counting up or down (saw-wave), counting up and down (triangle-wave) selectable for
all channels
Select from among four count clocks (PCLKA/1, PCLKA/4, PCLKA/8, and PCLKA/16)
for each channel
2 input/output pins per channel
2 output compare/input capture registers per channel
For the 2 output compare/input capture registers of each channel, 4 registers are
provided as buffer registers and are capable of operating as comparison registers when
buffering is not in use.
In output compare operation, buffer switching can be at peaks or troughs, enabling the
generation of laterally asymmetrically PWM waveforms.
Registers for setting up frame intervals on each channel (with capability for generating
interrupts on overflow or underflow)
Synchronizable operation of the several counters
Modes of synchronized operation (synchronized, or displaced by desired times for
phase shifting)
Generation of dead times in PWM operation
Through combination of three counters, generation of automatic three-phase PWM
waveforms incorporating dead times
Starting, clearing, and stopping counters in response to external or internal triggers
Internal trigger sources: Output of the internal comparator detection, software, and
compare-match
The main clock can be used as a counter clock for measuring the timing of the edges of
signals produced by frequency-dividing the dedicated clock signal for the IWDT (to
detect abnormal oscillation).
A PWM delay with an accuracy of up to 1/32 times the period of the system clock (ICLK)
can be generated to control the timing with which signals from the two PWM output pins
from each of channels 0 to 3 rise and fall.
(16 bits × 2 channels) × 2 units
Select from among four internal clock signals (PCLK/8, PCLK/32, PCLK/128, PCLK/
512)
14 bits × 1 channel
Select from among 6 counter-input clock signals (PCLK/4, PCLK/64, PCLK/128, PCLK/
512, PCLK/2048, PCLK/8192)
14 bits × 1 channel
Counter-input clock: Dedicated on-chip oscillator
Dedicated clock/1, dedicated clock/16, dedicated clock/32, dedicated clock/64,
dedicated clock/128, dedicated clock/256
Includes a UDC (USB Device Controller) and transceiver for USB 2.0
Single port
Compliance with the USB 2.0 specification
Transfer rate: Full speed (12 Mbps)
Self-power mode and bus power mode are selectable
Supports the OTG (On-The-Go)
Incorporates 2 Kbytes of RAM as a transfer buffer
Compare match timer
(CMT)
Watchdog timer
(WDTA)
Independent watchdog
timer (IWDTa)
Communication
function
USB 2.0 host/function
module (USBa)
Serial communications
interfaces (SCIc, SCId)
5 channels (SCIc: 4 channels + SCId: 1 channel)
SCIc
Serial communications modes: Asynchronous, clock synchronous, and smart-card
interface
Multi-processor function
On-chip baud rate generator allows selection of the desired bit rate
Choice of LSB-first or MSB-first transfer
Simple I
2
C
Simple SPI
SCId (The following functions are added to SCIc)
Supports the serial communications protocol, which contains the start frame and
information frame
Supports the LIN format
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Page 5 of 186
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