MCP37211-200
MCP37D11-200
200 Msps, 12-Bit Low-Power ADC with 8-Channel MUX
Features
• Sample Rates:
- 200 Msps for single-channel mode
- 200 Msps/number of channels used
• SNR with f
IN
= 15 MHz and -1 dBFS:
- 71.3 dBFS (typical) at 200 Msps
• SFDR with f
IN
= 15 MHz and -1 dBFS:
- 90 dBc (typical) at 200 Msps
• Power Dissipation with LVDS Digital I/O:
- 468 mW at 200 Msps
• Power Dissipation with CMOS Digital I/O:
- 436 mW at 200 Msps, Output Clock = 100 MHz
• Power Dissipation Excluding Digital I/O:
- 387 mW at 200 Msps
• Power-Saving Modes:
- 144 mW during Standby
- 28 mW during Shutdown
• Supply Voltage:
- Digital Section: 1.2V, 1.8V
- Analog Section: 1.2V, 1.8V
• Selectable Full-Scale Input Range: up to 2.975 V
P-P
• Input Channel Bandwidth: 500 MHz
• Channel-to-Channel Crosstalk in Multi-Channel
Mode (Input = 15 MHz, -1 dBFS): >95 dB
• Output Data Format:
- Parallel CMOS, DDR LVDS
• Optional Output Data Randomizer
• Serial Peripheral Interface (SPI)
• Digital Signal Post-Processing (DSPP) Options:
- Decimation filters for improved SNR
- Fractional Delay Recovery (FDR) for time-
delay corrections in multi-channel operations
(dual-/octal-channel modes)
- Noise-Shaping Requantizer (NSR)
- Phase, Offset and Gain adjust of individual
channels
- Digital Down-Conversion (DDC) with I/Q or
f
S
/8 output (MCP37D11-200)
- Continuous wave beamforming for octal-
channel mode (MCP37D11-200)
• Built-In ADC Linearity Calibration Algorithms:
- Harmonic Distortion Correction (HDC)
- DAC Noise Cancellation (DNC)
- Dynamic Element Matching (DEM)
- Flash Error Calibration
• AutoSync Mode to Synchronize Multiple Devices
to the Same Clock
• Package Options:
- VTLA-124 (9 mm x 9 mm x 0.9 mm)
- TFBGA-121 (8 mm x 8 mm x 1.08 mm)
• No External Reference Decoupling Capacitor
Required for TFBGA Package
• Industrial Temperature Range: -40°C to +85°C
Typical Applications
•
•
•
•
•
•
Communication Instruments
Microwave Digital Radio
Cellular Base Stations
Radar
Ultrasound and Sonar Imaging
Scanners and Low-Power Portable Instruments
MCP372XX/MCP37DXX Family Comparison
(1)
:
Part Number
MCP37231-200
MCP37221-200
MCP37211-200
MCP37D31-200
MCP37D21-200
MCP37D11-200
Note 1:
2:
3:
4:
Sample Rate
200 Msps
200 Msps
200 Msps
200 Msps
200 Msps
200 Msps
Resolution
16
14
12
16
14
12
Digital
CW
Digital
Decimation
(2)
Down-Conversion
(3)
Beamforming
(4)
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
Yes
Yes
Yes
No
No
No
Yes
Yes
Yes
Noise-Shaping
Requantizer
(2)
No
No
Yes
No
No
Yes
Devices in the same package type are pin-to-pin compatible.
Available in single- and dual-channel mode.
Available in single- and dual-channel mode, and octal-channel mode when CW beamforming is enabled.
Available in octal-channel mode.
2014-2016 Microchip Technology Inc.
DS20005355C-page 1
MCP37211-200 AND MCP37D11-200
Description
The MCP37211-200 is Microchip's baseline 12-bit
200 Msps pipelined ADC, featuring built-in high-order
digital decimation filters, noise-shaping requantizer,
gain and offset adjustment per channel and fractional
delay recovery.
The MCP37D11-200 device features digital down-
conversion and CW beamforming capability, in addition
to the features offered by the MCP37211-200.
All devices feature harmonic distortion correction and
DAC noise cancellation that enable high-performance
specifications with SNR of 71.3 dBFS (typical) and
SFDR of 90 dBc (typical).
These A/D converters exhibit industry-leading low-
power performance with only 468 mW operation while
using the LVDS interface at 200 Msps. This superior
low-power operation coupled with high dynamic
performance makes these devices ideal for various
high-performance, high-speed data acquisition
systems, including communications equipment, radar
and portable instrumentation.
In single or dual-channel mode, the Noise-Shaping
Requantizer (NSR) feature can allow the ADC to
improve SNR beyond a conventional 11- or 12-bit ADC.
The NSR reshapes the quantization noise, such that
most of the noise power is pushed outside the
frequency of interest. As a result, SNR is improved
significantly within a selected frequency band of
interest while SFDR is not affected.
The digital down-conversion option in the MCP37D10-
200 can be utilized with the decimation and quadrature
output (I and Q data) option, and offers great flexibility
in various digital communication system designs,
including cellular base-stations and narrow-band
communication systems.
The output decimation filter option improves SNR
performance up to 73.7 dBFS. The digital down-
conversion option, in conjunction with the decimation
and quadrature output options, offers great flexibility in
digital communication system design, including cellular
base-stations and narrow-band communications.
These devices can have up to eight differential input
channels through an input MUX. The sampling rate is
up to 200 Msps when a single channel is used, or
25 Msps per channel when all eight input channels are
used.
In dual or octal-channel mode, the Fractional Delay
Recovery (FDR) feature digitally corrects the difference
in sampling instance between different channels, so
that all inputs appear to have been sampled at the
same time.
AutoSync mode offers a great design flexibility when
multiple devices are used in applications. It allows
multiple devices to sample input synchronously at the
same clock.
The differential full-scale analog input range is
programmable up to 2.975 V
P-P
. The ADC output data
can be coded in two's complement or offset binary
representation, with or without the data randomizer
option. The output data is available as full-rate CMOS
or Double-Data-Rate (DDR) LVDS.
These devices also include various features designed
to maximize flexibility in the user’s applications and
minimize system cost, such as a programmable PLL
clock, output data rate control and phase alignment
and programmable digital pattern generation. The
device’s operational modes and feature sets are
configured by setting up the user-programmable
registers.
The device is available in Pb-free VTLA-124 and
TFBGA-121 packages. The device operates over the
commercial temperature range of -40°C to +85°C.
Package Types
Bottom View
Dimension:
9 mm x 9 mm x 0.9 mm
(a) VTLA-124 Package.
Bottom View
Dimension:
8 mm x 8 mm x 1.08 mm
Ball Pitch:
0.65 mm
Ball Diameter:
0.4 mm
(b) TFBGA-121 Package.
2014-2016 Microchip Technology Inc.
DS20005355C-page 3
京公网安备 11010802033920号
EEWORLD
