MTA144ASQ16G72LSZ-2S6E1 datasheet, PDF

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MTA144ASQ16G72LSZ-2S6E1: DescriptionMemory module DDR4 SDRAM 128GB LRDIMM 1.2V CL22; CategoryEmbedded solution Memory and data memory Memory modules, and memory card Memory module; File Size509KB，27 Pages; ManufacturerMicron; Websitehttp://www.micron.com/; Environmental Compliance

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MTA144ASQ16G72LSZ-2S6E1 Overview

Memory module DDR4 SDRAM 128GB LRDIMM 1.2V CL22

MTA144ASQ16G72LSZ-2S6E1 Parametric

Parameter Name	Attribute value
Maker	Micron
Product Category	memory module
product	LRDIMM
storage	128 GB
storage type	DDR4
speed	2666 MT/s
Working power voltage	1.2 V
Maximum operating temperature	+ 95 C
Number of pins	288 Pin
size	133.48 mm x 31.4 mm x 3.9 mm
Encapsulation	Tray
series	MTA144ASQ
Minimum operating temperature	0 C
Factory packaging quantity	100

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128GB (x72, ECC, 3DS 4H Stack, 2 Package Ranks x 4 Logic

Ranks) 288-Pin DDR4 LRDIMM

Features

DDR4 3DS SDRAM LRDIMM

MTA144ASQ16G72LSZ – 128GB

Features

• DDR4 functionality and operations supported as

defined in the component data sheet

• 288-pin, command/address/control registered, data

buffered, load-reduced dual in-line memory module

(LRDIMM)

• Fast data transfer rates: PC4-3200, PC4-2933, or

PC4-2666

• 128GB (16 Gig x 72)

• V

= 1.20V (NOM)

• V

= 2.5V (NOM)

• V

DDSPD

= 2.5V (NOM)

• Supports ECC error detection and correction

• Nominal and dynamic on-die termination (ODT) for

data, strobe, and mask signals

• Low-power auto self refresh (LPASR)

• On-die internal, adjustable, V

REFDQ

generation

• 2 package ranks x 4 logic ranks

• On-board I

C temperature sensor with integrated

serial presence-detect (SPD) EEPROM

• 32Gb, 3DS 4-high die stack x4 package, Master/Slave

control logic. Each die with 16 internal banks;

4 groups of 4 banks each

• Fixed burst chop (BC) of 4 and burst length (BL) of 8

via the mode register set (MRS)

• Selectable BC4 or BL8 on-the-fly (OTF)

• Gold edge contacts

• Halogen-free

• Fly-by topology

• Multiplexed command and address bus

• Terminated control, command and address bus

Table 1: Key Timing Parameters

Data Rate (MT/s)

CL =

Speed

Grade

-3S2

-2S9

PC4-

3200

2933

28 –

3200

–

RCD

Figure 1: 288-Pin LRDIMM (MO-309, R/C-B1)

Module height: 31.25mm (1.23in)

Options

• Operating temperature

– Commercial (0°C

≤

OPER

≤

95°C)

• Package

– 288-pin DIMM (halogen-free)

• Frequency/CAS latency

– 0.62ns @ CL = 26 (DDR4-3200)

– 0.682ns @ CL = 24 (DDR4-2933)

– 0.75ns @ CL = 22 (DDR4-2666)

Marking

None

-3S2

-2S9

-2S6

–

2933

–

2933

2666

2400

1600

(ns)

13.75

14.32

(ns)

13.75

14.32

(ns)

45.75

46.32

2133 2133 1866

CMTD-341111752-10426

asq144c16gx72lsz.pdf - Rev. C 3/18 EN

Products and specifications discussed herein are subject to change by Micron without notice.

Micron Technology, Inc. reserves the right to change products or specifications without notice.

128GB (x72, ECC, 3DS 4H Stack, 2 Package Ranks x 4 Logic

Ranks) 288-Pin DDR4 LRDIMM

Important Notes and Warnings

Micron Technology, Inc. ("Micron") reserves the right to make changes to information published in this document,

including without limitation specifications and product descriptions. This document supersedes and replaces all

information supplied prior to the publication hereof. You may not rely on any information set forth in this docu-

ment if you obtain the product described herein from any unauthorized distributor or other source not authorized

by Micron.

Automotive Applications.

Products are not designed or intended for use in automotive applications unless specifi-

cally designated by Micron as automotive-grade by their respective data sheets. Distributor and customer/distrib-

utor shall assume the sole risk and liability for and shall indemnify and hold Micron harmless against all claims,

costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of

product liability, personal injury, death, or property damage resulting directly or indirectly from any use of non-

automotive-grade products in automotive applications. Customer/distributor shall ensure that the terms and con-

ditions of sale between customer/distributor and any customer of distributor/customer (1) state that Micron

products are not designed or intended for use in automotive applications unless specifically designated by Micron

as automotive-grade by their respective data sheets and (2) require such customer of distributor/customer to in-

demnify and hold Micron harmless against all claims, costs, damages, and expenses and reasonable attorneys'

fees arising out of, directly or indirectly, any claim of product liability, personal injury, death, or property damage

resulting from any use of non-automotive-grade products in automotive applications.

Critical Applications.

Products are not authorized for use in applications in which failure of the Micron compo-

nent could result, directly or indirectly in death, personal injury, or severe property or environmental damage

("Critical Applications"). Customer must protect against death, personal injury, and severe property and environ-

mental damage by incorporating safety design measures into customer's applications to ensure that failure of the

Micron component will not result in such harms. Should customer or distributor purchase, use, or sell any Micron

component for any critical application, customer and distributor shall indemnify and hold harmless Micron and

its subsidiaries, subcontractors, and affiliates and the directors, officers, and employees of each against all claims,

costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of

product liability, personal injury, or death arising in any way out of such critical application, whether or not Mi-

cron or its subsidiaries, subcontractors, or affiliates were negligent in the design, manufacture, or warning of the

Micron product.

Customer Responsibility.

Customers are responsible for the design, manufacture, and operation of their systems,

applications, and products using Micron products. ALL SEMICONDUCTOR PRODUCTS HAVE INHERENT FAIL-

URE RATES AND LIMITED USEFUL LIVES. IT IS THE CUSTOMER'S SOLE RESPONSIBILITY TO DETERMINE

WHETHER THE MICRON PRODUCT IS SUITABLE AND FIT FOR THE CUSTOMER'S SYSTEM, APPLICATION, OR

PRODUCT. Customers must ensure that adequate design, manufacturing, and operating safeguards are included

in customer's applications and products to eliminate the risk that personal injury, death, or severe property or en-

vironmental damages will result from failure of any semiconductor component.

Limited Warranty.

In no event shall Micron be liable for any indirect, incidental, punitive, special or consequential

damages (including without limitation lost profits, lost savings, business interruption, costs related to the removal

or replacement of any products or rework charges) whether or not such damages are based on tort, warranty,

breach of contract or other legal theory, unless explicitly stated in a written agreement executed by Micron's duly

authorized representative.

CMTD-341111752-10426

asq144c16gx72lsz.pdf - Rev. C 3/18 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

128GB (x72, ECC, 3DS 4H Stack, 2 Package Ranks x 4 Logic

Ranks) 288-Pin DDR4 LRDIMM

Pin Descriptions

The pin description table below is a comprehensive list of all possible pins for DDR4

modules. All pins listed may not be supported on this module. See Functional Block Di-

agram for pins specific to this module.

Table 5: Pin Descriptions

Symbol

Type

Input

Description

Address inputs:

Provide the row address for ACTIVATE commands and the column address for

READ/WRITE commands in order to select one location out of the memory array in the respec-

tive bank (A10/AP, A12/BC_n, WE_n/A14, CAS_n/A15, and RAS_n/A16 have additional functions;

see individual entries in this table). The address inputs also provide the op-code during the

MODE REGISTER SET command. A17 is only defined for x4 SDRAM.

Auto precharge:

A10 is sampled during READ and WRITE commands to determine whether an

auto precharge should be performed on the accessed bank after a READ or WRITE operation

(HIGH = auto precharge; LOW = no auto precharge). A10 is sampled during a PRECHARGE com-

mand to determine whether the precharge applies to one bank (A10 LOW) or all banks (A10

HIGH). If only one bank is to be precharged, the bank is selected by the bank group and bank

addresses.

Burst chop:

A12/BC_n is sampled during READ and WRITE commands to determine if burst

chop (on-the-fly) will be performed (HIGH = no burst chop; LOW = burst chopped). See Com-

mand Truth Table in the DDR4 component data sheet.

Command input:

ACT_n defines the ACTIVATE command being entered along with CS_n. The

input into RAS_n/A16, CAS_n/A15, and WE_n/A14 are considered as row address A16, A15, and

A14. See Command Truth Table.

Bank address inputs:

Define the bank (with a bank group) to which an ACTIVATE, READ,

WRITE, or PRECHARGE command is being applied. Also determine which mode register is to be

accessed during a MODE REGISTER SET command.

Bank group address inputs:

Define the bank group to which a REFRESH, ACTIVATE, READ,

WRITE, or PRECHARGE command is being applied. Also determine which mode register is to be

accessed during a MODE REGISTER SET command. BG[1:0] are used in the x4 and x8 configura-

tions. x16-based SDRAM only has BG0.

Chip ID:

These inputs are used only when devices are stacked; that is, 2H, 4H, and 8H stacks for

x4 and x8 configurations using through-silicon vias (TSVs). These pins are not used in the x16

configuration. Some DDR4 modules support a traditional DDP package, which uses CS1_n,

CKE1, and ODT1 to control the second die. All other stack configurations, such as a 4H or 8H,

are assumed to be single-load (master/slave) type configurations where C0, C1, and C2 are used

as chip ID selects in conjunction with a single CS_n, CKE, and ODT. Chip ID is considered part of

the command code.

Clock:

Differential clock inputs. All address, command, and control input signals are sampled

on the crossing of the positive edge of CK_t and the negative edge of CK_c.

Clock enable:

CKE HIGH activates and CKE LOW deactivates the internal clock signals, device

input buffers, and output drivers. Taking CKE LOW provides PRECHARGE POWER-DOWN and

SELF REFRESH operations (all banks idle), or active power-down (row active in any bank). CKE is

asynchronous for self refresh exit. After V

REFCA

has become stable during the power-on and ini-

tialization sequence, it must be maintained during all operations (including SELF REFRESH). CKE

must be maintained HIGH throughout read and write accesses. Input buffers (excluding CK_t,

CK_c, ODT, RESET_n, and CKE) are disabled during power-down. Input buffers (excluding CKE

and RESET_n) are disabled during self refresh.

Chip select:

All commands are masked when CS_n is registered HIGH. CS_n provides external

rank selection on systems with multiple ranks. CS_n is considered part of the command code

(CS2_n and CS3_n are not used on UDIMMs).

A10/AP

Input

A12/BC_n

Input

ACT_n

Input

BAx

Input

BGx

Input

C0, C1, C2

(RDIMM/LRDIMM on-

ly)

Input

CKx_t

CKx_c

CKEx

Input

CSx_n

Input

CMTD-341111752-10426

asq144c16gx72lsz.pdf - Rev. C 3/18 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

MTA144ASQ16G72LSZ-2S6E1 Related Products

	MTA144ASQ16G72LSZ-2S6E1	MTA144ASQ16G72LSZ-2S9E1
Description	Memory module DDR4 SDRAM 128GB LRDIMM 1.2V CL22	Memory module DDR4 SDRAM 128GB LRDIMM 1.2V CL22
Maker	Micron	Micron
Product Category	memory module	memory module
product	LRDIMM	LRDIMM
storage	128 GB	128 GB
storage type	DDR4	DDR4
speed	2666 MT/s	2933 MT/s
Working power voltage	1.2 V	1.2 V
Maximum operating temperature	+ 95 C	+ 95 C
Number of pins	288 Pin	288 Pin
size	133.48 mm x 31.4 mm x 3.9 mm	133.48 mm x 31.4 mm x 3.9 mm
Encapsulation	Tray	Tray
series	MTA144ASQ	MTA144ASQ
Minimum operating temperature	0 C	0 C
Factory packaging quantity	100	100

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