NXP Semiconductors
Data Sheet: Technical Data
Document Number LS1088A
Rev. 0, 01/2018
QorIQ LS1088A Data Sheet
Features
• LS1088A contains eight ARM® Cortex®-A53 (32/64
bit) cores with the following capabilities:
– Speed up to 1.6 GHz
– Arranged as two clusters of four cores
– 32 KB L1 instruction cache (ECC protection) and 32
KB L1 data cache (ECC protection)
– Two 1 MB unified I/D L2 cache (ECC protection),
one per Cortex-A53 core cluster
– NEON™ SIMD coprocessor
– ARMv8 cryptography extensions
• Hierarchical interconnect fabric:
– Hardware-managed data coherency
– Up to 700 MHz operation
• One 32/64-bit DDR4 SDRAM memory controller:
– ECC and interleaving support
– Up to 2.1 GT/s
• Datapath acceleration architecture 2.0 (DPAA2)
incorporates acceleration for the following functions:
– Packet parsing, classification, and distribution
(WRIOP)
– Queue management for scheduling, packet
sequencing, and congestion management (QMan)
– Hardware buffer management for buffer allocation
and de-allocation (BMan)
– Cryptography acceleration (SEC)
– IEEE 1588 support
– Advanced I/O processor (AIOP)
• Parallel Ethernet interfaces:
– Up to two RGMII interfaces
LS1088A
• Eight SerDes lanes for high-speed peripheral
interfaces:
– Three PCI Express 3.0 controllers (one supporting
x4 operation)
– One serial ATA (SATA 3.0) controller supporting
6 Gbps
– Up to two SGMII supporting 2500 Mbps
– Up to four SGMII supporting 1000 Mbps
– Up to two XFI (10 GbE) interfaces
– Up to two QSGMII
– Supports 1000Base-KX
– Supports 10GBase-KR
• Additional peripheral interfaces include:
– One quad serial peripheral interface (QSPI)
controller, one serial peripheral interface (SPI)
controller
– Integrated flash controller (IFC) supporting NAND
and NOR flash with 28-bit addressing and 16-bit
data
– Two USB 3.0 controllers with integrated PHY
– Enhanced secure digital host controller supporting
SD 3.0, eMMC 4.4, and eMMC 4.5 modes
– uQE supporting TDM/HDLC
– Four I2C controllers
– Two 16550-compliant DUARTs
– General purpose IO (GPIO), four FlexTimers, and
nine watchdog timers
– Trust architecture
– Debug support with run control, data acquisition,
high-speed trace, and performance/event monitoring
• 780 FC-PBGA package, 23 mm x 23 mm, 0.8 mm
pitch
NXP reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products.
Table of Contents
1 Overview.............................................................................................. 3
2 Pin assignments.................................................................................... 3
2.1
2.2
780 BGA ball layout diagrams.................................................. 4
Pinout list...................................................................................10
3.17 I2C interface.............................................................................. 144
3.18 Integrated Flash Controller........................................................147
3.19 JTAG interface.......................................................................... 166
3.20 Quad serial peripheral interface (QuadSPI).............................. 169
3.21 QUICC engine specifications.................................................... 173
3.22 Serial peripheral interface (SPI)................................................ 179
3.23 Universal serial bus (USB) interface.........................................182
4 Hardware design considerations...........................................................185
4.1
4.2
Clock ranges.............................................................................. 185
Power supply design..................................................................186
3 Electrical characteristics.......................................................................51
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
Overall DC electrical characteristics......................................... 51
General AC timing specifications............................................. 57
Power sequencing......................................................................58
Power-down requirements.........................................................61
Power characteristics................................................................. 61
Power-on ramp rate................................................................... 63
Input clocks............................................................................... 63
RESET initialization timing specifications............................... 70
Battery-backed security monitor interface................................ 71
5 Thermal................................................................................................ 187
5.1
5.2
5.3
Recommended thermal model...................................................188
Temperature diode.....................................................................188
Thermal management information............................................ 188
3.10 DDR4 SDRAM controller.........................................................72
3.11 Dual universal asynchronous receiver/transmitter (DUART)
interface..................................................................................... 77
3.12 Enhanced secure digital host controller (eSDHC).....................79
3.13 Ethernet interface (EMI, RGMII, and IEEE Std 1588)............. 87
3.14 General purpose input/output (GPIO) interface........................ 97
3.15 Generic interrupt controller (GIC) interface..............................101
3.16 High-speed serial interfaces (HSSI).......................................... 103
6 Package information.............................................................................191
6.1
6.2
Package parameters for the FC-PBGA......................................191
Mechanical dimensions of the FC-PBGA................................. 191
7 Security fuse processor.........................................................................193
8 Ordering information............................................................................193
8.1
8.2
Part numbering nomenclature....................................................193
Part marking ............................................................................. 194
9 Revision history....................................................................................195
QorIQ LS1088A Data Sheet, Rev. 0, 01/2018
2
NXP Semiconductors
Overview
1 Overview
A member of the Layerscape (LS1) series, the LS1088A is a cost-effective, power-
efficient, and highly integrated system-on-chip (SoC) device featuring eight extremely
power-efficient 64-bit ARM® Cortex®-A53 cores with ECC-protected L1 and L2 cache
memories for high reliability, running up to 1.6 GHz.
The LS1088A family of devices can be used for enterprise and service provider routers,
Virtual CPE, industrial communications, security appliance and military and aerospace
applications.
This figure shows the LS1088A block diagram.
Arm® Cortex®
Arm Cortex-
Arm Cortex-
A53 64b Core
A53 64b Cores
A53 64b Cores
Arm Cortex-
A53 64b Cores
Arm Cortex-
Arm® Cortex®
Arm Cortex-
Arm Cortex-
A53 64b Core
A53 64b Cores
A53 64b Cores
Arm Cortex-
A53 64b Cores
Arm Cortex-
32 KB
32 KB
D-Cache
32 KB
32 KB
A53 64b32 KB
Cores
I-Cache
32 KB
I-Cache
D-Cache
I-Cache
D-Cache
32 KB
32 KB
I-Cache
D-Cache
1 MB L2 - Cache
32 KB
32 KB
D-Cache
32 KB
32 KB
A53 64b32 KB
Cores
I-Cache
32 KB
I-Cache
D-Cache
I-Cache
D-Cache
32 KB
32 KB
I-Cache
D-Cache
1 MB L2 - Cache
64-bit
DDR4
Memory Controller
Secure Boot
Trust Zone
Power Management
IFC, QuadSPI, SPI
SD/SDIO/eMMC
2x DUART
4x I2C, GPIO
4x FlexTimer
2x USB3.0 w/PHY
qDMA
DPAA2 Hardware
Core Complex
Accelerators and Memory Control
Basic Peripherals, Interconnect and Debug
Networking Elements
Security
Engine
(SEC)
Queue /
Buffer
Manager
Buffer
CCI-400™ Coherency Fabric
SMMUs
Management Complex
WRIOP
Real Time Debug
PCIe 3.0
PCIe 3.0
SATA 3.0
PCIe 3.0
Buffering
1G
1G
1G
1G
1G
1G
1G
1G
Advanced
IO
Processor
(AIOP)
uQE
Watchpoint
Cross
Trigger
Perf
Monitor
Trace
1/10G
1/10G
4-Lane 10 GHz SerDes
4-Lane 10 GHz SerDes
Figure 1. LS1088A block diagram
2 Pin assignments
NOTE:
Information given in this section is preliminary and is subject to change.
QorIQ LS1088A Data Sheet, Rev. 0, 01/2018
NXP Semiconductors
3
Pin assignments
2.1 780 BGA ball layout diagrams
This figure shows the complete view of the LS1088A BGA ball map diagram.
Figure 3,
Figure 4, Figure 5,
and
Figure 6
show quadrant views.
QorIQ LS1088A Data Sheet, Rev. 0, 01/2018
4
NXP Semiconductors
Pin assignments
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
A
B
C
D
E
SEE DETAIL A
SEE DETAIL B
F
G
H
J
K
L
M
N
P
R
T
U
V
W
SEE DETAIL C
SEE DETAIL D
Y
AA
AB
AC
AD
AE
AF
AG
AH
DDRC1
IFC1
UART1
UART2
I2C1
I2C2
I2C
DSPI1
ESDHC1
GIC500
Debug
SNVS
System Control
Clocking
DDR Clocking
DFT
JTAG
Analog Signals
Serdes 1
Serdes 2
USB3 PHY 1
USB3 PHY 2
USB
EMI1
EMI2
EC1
EC2
Power
Ground
No Connects
Figure 2. Complete BGA Map for the LS1088A
QorIQ LS1088A Data Sheet, Rev. 0, 01/2018
NXP Semiconductors
5
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