Features ................................................................................................................................................................ 4
LPDDR3 MC Module............................................................................................................................................. 7
PHY Control Block ....................................................................................................................................... 8
Data Path Logic............................................................................................................................................ 8
Signal Descriptions ............................................................................................................................................... 9
Using the Local User Interface............................................................................................................................ 11
Command and Address ............................................................................................................................. 12
User Commands ........................................................................................................................................ 14
REFRESH Support .................................................................................................................................... 16
Type Tab ............................................................................................................................................................. 21
Memory Type ............................................................................................................................................. 21
Memory Data Bus Size .............................................................................................................................. 21
Refresh Bank ............................................................................................................................................. 23
Auto Refresh Burst Count .......................................................................................................................... 23
External Auto Refresh Port ........................................................................................................................ 23
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
Chapter 4. IP Core Generation and Evaluation .................................................................................. 26
Getting Started .................................................................................................................................................... 26
Clarity Designer-Created Files and IP Top Level Directory Structure................................................................. 29
LPDDR3 Memory Controller IP File Structure............................................................................................ 31
Simulation Files for IP Evaluation .............................................................................................................. 32
Enabling Hardware Evaluation in Diamond:............................................................................................... 33
Regenerating/Recreating the IP Core ................................................................................................................. 33
Regenerating an IP Core in Clarity Designer Tool ..................................................................................... 33
Recreating an IP Core in Clarity Designer Tool ......................................................................................... 33
FREQUENCY Preferences ........................................................................................................................ 35
MAXDELAY NET ....................................................................................................................................... 35
E-mail Support ........................................................................................................................................... 38
Local Support ............................................................................................................................................. 38
Internet ....................................................................................................................................................... 38
Revision History .................................................................................................................................................. 38
Appendix A. Resource Utilization ....................................................................................................... 39
Ordering Part Number................................................................................................................................ 39
IPUG110_1.0, September 2014
3
LPDDR3 SDRAM Controller IP Core User’s Guide
Chapter 1:
Introduction
The Lattice Low Power Double Data Rate (LPDDR3) Synchronous Dynamic Random Access Memory (SDRAM)
Controller is a general-purpose memory controller that interfaces with industry standard LPDDR3 memory devices
compliant with JESD209-3,
LPDDR3 SDRAM Standard,
and provides a generic command interface to user appli-
cations. LPDDR3 SDRAM is the next-generation Low Power SDRAM memory technology which offers a higher
data rate, higher density, greater bandwidth and power efficiency. This core reduces the effort required to integrate
the LPDDR3 memory controller with the user application design and minimizes the need to directly deal with the
LPDDR3 memory interface.
Quick Facts
Table 1-1
gives quick facts about the LPDDR3 SDRAM Controller IP core.
Table 1-1. LPDDR3 IP Core Quick Facts
1
LPDDR3 IP Configuration
x16
Core
Requirements
FPGA Families
Supported
Minimal Device
Needed
Resource
Utilization
Targeted Device
Data Path Width
LUTs
sysMEM EBRs
Registers
Design Tool
Support
Lattice
Implementation
Synthesis
Simulation
1599
Lattice Diamond
®
3.3
Synopsys
®
Synplify Pro
®
for Lattice I-2014.03L-SP1
Lattice Synthesis Engine (LSE)
Aldec
®
Active-HDL
®
9.3 Lattice Edition II Mixed Language
Mentor Graphics
®
ModelSim
®
SE PLUS 6.5 or later
1. LFE5U-25F-6MG381C/LAE5UM-25F-6MG381E for the core evaluation project inside a generated core
x32
ECP5
™
LFE5U-25F-6MG285C/
LAE5UM-25F-6MG285E
LFE5U-25F-6MG285C/
LAE5UM-25F-6MG285E
1
LFE5UM-85F-8BG756CES
16
2241
0
1937
32
2462
Features
The LPDDR3 SDRAM Controller IP core supports the following features:
• Support for all ECP5 devices
• Interfaces to industry standard LPDDR3 SDRAM components and modules compliant with JESD209-3,
LPDDR3 SDRAM Standard
• Interfaces to LPDDR3 SDRAM at speeds up to 400 MHz / 800 Mbps in -8 speed grade devices
• Supports memory data path widths of 16 and 32 bits
• Supports x16 and x32 device configurations
• Supports single rank of an LPDDR3 device (one chip select)
• Supports burst lengths of eight (fixed)
IPUG110_1.0, September 2014
4
LPDDR3 SDRAM Controller IP Core User’s Guide
Introduction
• Programmable read and write latency set
• Supports automatic LPDDR3 SDRAM initialization and refresh
• Optional write leveling support for each DQS
• Automatic read training for each DQS
• Supports Deep Power Down mode and Power down mode
• Supports Partial Array Self Refresh (PASR) operations on Bank and Segment
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