Features ....................................................................................................................................................... 4
Control and Status ....................................................................................................................................... 6
Buffer Status Mode ...................................................................................................................................... 8
AUXCTRL and AUXSTAT............................................................................................................................ 9
System Configurations ............................................................................................................................... 11
Registers and Memory ............................................................................................................................... 15
User Parameters Tab.......................................................................................................................................... 23
Transfer Settings........................................................................................................................................ 26
Chapter 4. IP Core Generation............................................................................................................. 28
IP Core Generation in IPexpress ........................................................................................................................ 28
Licensing the IP Core................................................................................................................................. 28
Getting Started ........................................................................................................................................... 28
IPexpress-Created Files and Top Level Directory Structure...................................................................... 30
IP Core Implementation ............................................................................................................................. 33
Updating/Regenerating the IP Core ........................................................................................................... 34
IP Core Generation in Clarity Designer............................................................................................................... 35
Getting Started ........................................................................................................................................... 35
Clarity Designer Created Files and Top Level Directory Structure ............................................................ 39
IP Core Implementation ............................................................................................................................. 40
Regenerating/Recreating the IP Core ................................................................................................................. 41
Regenerating an IP Core in Clarity Designer Tool ..................................................................................... 41
Recreating an IP Core in Clarity Designer Tool ......................................................................................... 41
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
IPUG67_1.8, March 2015
2
Scatter-Gather DMAC User Guide
Table of Contents
Chapter 5. Support Resources ............................................................................................................ 42
E-mail Support ........................................................................................................................................... 42
Local Support ............................................................................................................................................. 42
Internet ....................................................................................................................................................... 42
Revision History .................................................................................................................................................. 43
Appendix A. Resource Utilization ....................................................................................................... 44
Ordering Part Number................................................................................................................................ 44
Ordering Part Number................................................................................................................................ 44
Ordering Part Number................................................................................................................................ 44
Ordering Part Number................................................................................................................................ 45
IPUG67_1.8, March 2015
3
Scatter-Gather DMAC User Guide
Chapter 1:
Introduction
This user guide describes the Scatter-Gather Direct Memory Access Controller (SGDMAC) IP core for the ECP5™,
LatticeECP3™ and LatticeXP2™ families of devices. The Lattice SGDMAC core implements a configurable, multi-
channel, WISHBONE-compliant DMA controller with scatter-gather capability. Directions for specifying the IP
core’s configuration, including it in a user’s design, and directions for simulation and synthesis are provided in this
user’s guide.
Quick Facts
Table 1-1 gives quick facts about the Scatter-Gather DMA Controller IP core.
Table 1-1. Scatter-Gather DMA Controller IP Core Quick Facts
SGDMAC IP Configuration
16 Channel,
Dual-bus
Core
Requirements
FPGA Families
Supported
Targeted Device
Data Path Width
Resource
Utilization
LUTs
Slices
Registers
FMAX (MHz)
Lattice Implementation
Design Tool
Support
Synthesis
Simulation
LFE3-95EA-7FN672C
4 channel,
Dual-bus
8 channel,
Dual-bus
4 channel,
Dual-bus
LatticeECP3, LatticeXP2, ECP5
LFXP2-40E-6F672C
LFE5U-85F-8BG756C LFE5UM-85F-8BG756C
32
4311
2670
1932
145
32
3443
2139
1355
120
32/64
4049
2570
1637
160
32/8
3222
1998
1265
165
Lattice Diamond
®
3.4
Synopsys
®
Synplify Pro
®
for Lattice J-2014.09L
Mentor Graphics
®
Precision
®
RTL
Aldec
®
Active-HDL™ 9.3 SPI Lattice Edition
Mentor Graphics
®
ModelSim
®
SE 6.6e or later
Features
• Supports up to 16 physical channels
• Up to 8 sub-channels per physical channel
• Four priority levels using round-robin arbitration (weighted or simple)
• WISHBONE bus widths from 8 to 128 bits
• Simple DMA, split transfers, scatter-gather
• Direct interface to external RAM for packet buffering
• Autonomous and hardware-directed retry
• Supports WISHBONE burst and classic-cycle transfers
• Supports centralized and distributed DMA control architectures
IPUG67_1.8, March 2015
4
Scatter-Gather DMAC User Guide
Chapter 2:
Functional Description
This chapter provides a functional description of the Scatter-Gather DMA Controller core.
Key Concepts
Direct Memory Access (DMA)
is a technique for transferring blocks of data between system memory and periph-
erals without a processor (e.g., system CPU) having to be involved in each transfer. DMA not only offloads a sys-
tem’s processing elements, but can transfer data at much higher rates than processor reads and writes.
Scatter-Gather DMA
provides data transfers from one non-contiguous block of memory to another by means of a
series of smaller contiguous-block transfers.
Buffer Descriptors
hold the necessary control information for data transfers:
• Source and destination buses and addresses
• Amount of data to be transferred and maximum burst size
• Addressing modes, bus sizes, transaction types, retry options, etc.
Buffer descriptors may be chained together to provide scatter-gather capability.
A
DMA Channel
consists of:
• A set of Buffer Descriptors describing the transfers associated with the channel
• Control and status registers for initiating/observing the transfer process
• An interface to allow the DMA engine access to the channel control and status
• An optional external DMA request/acknowledge signal pair for hardware initiated transfers
• A signal for indicating a pending DMA request to the DMA controller’s arbiter and engine
The SGDMAC core provides DMA transfers of data between WISHBONE bus slaves for up to 16 physical DMA
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