DATASHEET
HS-82C54RH
Radiation Hardened CMOS Programmable Interval Timer
The Intersil HS-82C54RH is a high performance, radiation
hardened CMOS version of the industry standard 8254 and
is manufactured using a hardened field, self-aligned silicon
gate CMOS process. It has three independently
programmable and functional 16-bit counters, each capable
of handling clock input frequencies of up to 5MHz. Six
programmable timer modes allow the HS-82C54RH to be
used as an event counter, elapsed time indicator, a
programmable one-shot, or for any other timing application.
The high performance, radiation hardness, and industry
standard configuration of the HS-82C54RH make it
compatible with the HS-80C86RH radiation hardened
microprocessor.
Static CMOS circuit design insures low operating power. The
Intersil hardened field CMOS process results in performance
equal to or greater than existing radiation resistant products
at a fraction of the power.
Specifications for Rad Hard QML devices are controlled
by the Defense Supply Center in Columbus (DSCC). The
SMD numbers listed here must be used when ordering.
Detailed Electrical Specifications for these devices are
contained in SMD 5962-95713. A “hot-link” is provided
on our homepage for downloading.
www.intersil.com/spacedefense/space.asp
Data Sheet
August 2000
FN3043
Rev 2.00
Aug 2000
Features
• Electrically Screened to SMD # 5962-95713
• QML Qualified per MIL-PRF-38535 Requirements
• Radiation Performance
- Total Dose. . . . . . . . . . . . . . . . . . . . . 100 krad(Si) (Max)
- Transient Upset . . . . . . . . . . . . . . . . . . . .>10
8
rad(Si)/s
- Latch Up Free EPI-CMOS
• Low Power Consumption
- IDDSB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20A
- IDDOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12mA
• Pin Compatible with NMOS 8254 and the Intersil 82C54
• High Speed, “No Wait State” Operation with 5MHz
HS-80C86RH
• Three Independent 16-Bit Counters
• Six Programmable Counter Modes
• Binary or BCD Counting
• Status Read Back Command
• Hardened Field, Self-Aligned, Junction Isolated CMOS
Process
• Single 5V Supply
• Military Temperature Range . . . . . . . . . . . -55
o
C to 125
o
C
Ordering Information
ORDERING NUMBER
5962R9571301QJC
5962R9571301QXC
5962R9571301VJC
INTERNAL
MKT. NUMBER
HS1-82C54RH-8
HS9-82C54RH-8
HS1-82C54RH-Q
TEMP. RANGE
(
o
C)
-55 to 125
-55 to 125
-55 to 125
FN3043 Rev 2.00
Aug 2000
Page 1 of 17
HS-82C54RH
Pinouts
24 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE
(SBDIP) MIL-STD-1835 CDIP2-T24
TOP VIEW
D7 1
D6 2
D5 3
D4 4
D3 5
D2 6
D1 7
D0 8
CLK 0 9
OUT 0 10
GATE 0 11
GND 12
24 VDD
23 WR
22 RD
21 CS
20 A1
19 A0
18 CLK 2
17 OUT 2
16 GATE 2
15 CLK 1
14 GATE 1
13 OUT 1
24 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
(FLATPACK) MIL-STD-1835 CDFP4-F24
TOP VIEW
D7
D6
D5
D4
D3
D2
D1
D0
CLK 0
OUT 0
GATE 0
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VDD
WR
RD
CS
A1
A0
CLK 2
OUT 2
GATE 2
CLK 1
GATE 1
OUT1
Pin Descriptions
SYMBOL
D7-D0
CLK 0
OUT 0
GATE 0
GND
OUT 1
GATE 1
CLK 1
GATE 2
OUT 2
CLK 2
A0, A1
PIN
NUMBER
1-8
9
10
11
12
13
14
15
16
17
18
19-20
O
I
I
I
O
I
I
TYPE
I/O
I
O
I
DESCRIPTION
DATA: Bi-directional three state data bus lines, connected to system data bus.
CLOCK 0: Clock input of Counter 0.
OUT 0: Output of Counter 0.
GATE 0: Gate input of Counter 0.
GROUND: Power supply connection.
OUT 1: Output of Counter 1.
GATE 1: Gate input of Counter 1.
CLOCK 1: Clock input of Counter 1.
GATE 2: Gate input of Counter 2.
OUT 2: Output of Counter 2.
CLOCK 2: Clock input of Counter 2.
ADDRESS: Select inputs for one of the three counters or Control Word Register for read/write
operations. Normally connected to the system address bus.
A1
0
0
1
1
CS
RD
WR
VDD
21
22
23
24
I
I
I
A0
0
1
0
1
Selects
Counter 0
Counter 1
Counter 2
Control Word Register
CHIP SELECT: A low on this input enables the HS-82C54RH to respond to RD and WR signals. RD
and WR are ignored otherwise.
READ: This input is low during CPU read operations.
WRITE: This input is low during CPU write operations.
VDD: The +5V power supply pin. A 0.1F capacitor between pins 12 and 24 is recommended for
decoupling.
FN3043 Rev 2.00
Aug 2000
Page 2 of 17
HS-82C54RH
Burn-In Circuits
STATIC CONFIGURATION FOR BOTH
FLATPACK AND SBDIP PACKAGE
VDD
F3
F4
F5
F6
F7
F8
F9
F0
OPEN
F10
F1
LOAD
F11
OPEN
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
LOAD
LOAD
2.7k
LOAD
VDD
2.7k
F2
F0
F0
DYNAMIC CONFIGURATION FOR BOTH
FLATPACK AND SBDIP PACKAGE
VDD
1
2
3
4
5
6
7
8
F0
OPEN
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
NOTES:
1. VDD = 6.5V
5%
2. T
A
= 125
o
C Minimum
3. Resistors = 10k
4. IDD < 100A
5. AC: F0 is compliment of F0
F0 is a 50% duty cycle pulse burst
F0 is left high after pulse burst
NOTES:
6. VDD = 6.5V
5%
(Burn-In)
7. VDD = 6.0V
5%
(Life Test)
8. T
A
= 125
o
C Minimum
9. IDD < 20mA
10. Resistors = 10kexcept for loads = 2.7k
11. -0.3V
VIL
0.8V
12. VDD -1.0V
VIH
VDD +0.5V
13. AC: F0 is compliment of F0
F0 = 100kHz
10%,
50% Duty Cycle
F1 = F0/2, F2 = F1/2 . . . F10 = F9/2
Irradiation Circuits
HS-82C54RH
1
2
3
4
5
5.5V
6
7
8
9
N/C
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
N/C
N/C
5.5V
NOTES:
14. VDD = 5.5V
10%,
T
A
= 25
o
C
15. Group E Testing is performed in Sidebrazed DIP
16. Group E Sample Size is 2 die/wafer
FN3043 Rev 2.00
Aug 2000
Page 5 of 17
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